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128 kb dual-port sram with pci bus controller (pci-dp) CY7C09449PV-ac cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-06061 rev. *a revised december 27, 2002 09449pv features ? 128 kb of dual-ported shared memory master and target pci specification 2.2 compliant in- terface embedded host bridge capability direct interface to many microprocessors i 2 o message transport unit; includes four 32-bit, 32- entry fifo local bus clock rates up to 50 mhz single 3.3v power supply including compatibility with 3v and 5v pci bus signaling 160-pin thin plastic quad flat package introduction the CY7C09449PV is one of the pci interface controllers in the cypress semiconductor pci-dp ? family. the CY7C09449PV provides a pci master/target interface with di- rect connections to many popular microprocessors. it provides 128 kb of dual-port sram that is used as shared memory between the local microprocessor and the pci bus. an i 2 o message unit, complete with message queues and interrupt capability, is also provided. the CY7C09449PV allows the de- signer to interface an application to the pci bus in a straight- forward, inexpensive way. functional overview the CY7C09449PV is composed of a number of shared re- sources that allow effective data movement between the local bus and the pci bus. a primary resource within the CY7C09449PV is its 128 kb of dual-port memory. this memory is interfaced to both the pci bus and to a local microprocessor bus. this shared memory can be accessed as a target from both buses at the same time for inter-process communication. from either the local or pci bus the CY7C09449PV can be directed to become a pci bus master to move data into or out of the internal shared memory as a direct memory access (dma). the CY7C09449PV can dma across the pci bus any number of 32-bit double words (dword), up to 16k bytes. it uses the full bursting capabilities of the pci bus for maximum efficiency and can transfer data over the full 32-bit pci address space. the CY7C09449PV implements optional requirements of the pci specification by selecting the optimum pci command for each transaction it masters to the pci bus. this maximizes overall efficiency of the system platform. pci bridging func- tions (pci-to-pci and host-to-pci bridges) use the commands to enhance prefetch and cache coherency operations. the CY7C09449PV requests and gains access to the pci bus as any master. it does not, within itself, include a pci bus arbitra- tion function. standard pc pci buses include this function; embedded systems may need to implement this function. the CY7C09449PV provides a direct access mechanism from the local bus to the pci bus. with it, the local processor can direct the CY7C09449PV to run a pci bus master cycle of any kind to any address. this means that the CY7C09449PV can run pci configuration cycles allowing it to be used as a host bridge. table of contents features 1 introduction 1 functional overview 1 pin configuration 4 pin description 5 pci bus 9 local bus 12 timing diagrams 16 i 2 c serial port and auto-configuration 27 operations registers 29 performance characteristics 41 CY7C09449PV operations 46 ordering information 48 package diagram 48
CY7C09449PV-ac document #: 38-06061 rev. *a page 2 of 50 four first-in first-out (fifo) storage elements provide anoth- er resource to the user. these are accessible from either the pci bus or the local bus. when the i 2 o messaging unit func- tionality of the CY7C09449PV is to be used, the four fifos become part of the i 2 o messaging unit of the CY7C09449PV. the i 2 o messaging unit consists of the four fifos and the i 2 o system interrupt registers. the shared memory of the CY7C09449PV may be used to store i 2 o message frame buff- ers while most of shared memory is still available for generals purpose use. efficient i 2 o messaging is realized when the lo- cal processor uses the CY7C09449PV direct access mecha- nism. it can be used to retrieve and post i 2 o message pointers to other i 2 o agents. data transfer of the messages themselves is made very efficient using the CY7C09449PV pci dma con- troller to burst the message frames to other i 2 o agents. interprocess communication is supported by two resources of the CY7C09449PV: the mailbox registers and the arbitration flags. by writing to the mailbox registers, a method is available for the local processor to pass data while causing an interrupt to the host, and vice versa. this is enabled by the interrupt mask located in the CY7C09449PV operations registers. the arbitration flags are four pairs of bits that can be used to man- age resource allocation and sharing between software and system processes. the CY7C09449PV includes an interrupt controller. there are separate interrupt mask and command/status registers for the pci bus and the local bus. the interrupt sources are dma completion, mailbox, fifo not empty (also for i 2 o), fifo over- flow, pci master abort, pci target abort, and there is an exter- nal interrupt input pin. this interrupt controller is used to signal interrupts onto the pci bus and the local bus. the CY7C09449PV interrupt controller does not perform the inter- rupt controller function for the pci bus system. standard pc pci systems include this function; embedded systems may need to implement this function. an i 2 c-compatible serial interface is provided to allow the use of a serial eeprom for non-volatile storage of CY7C09449PV initialization parameters. the parameters are pci configura- tion and local bus settings. the CY7C09449PV will optionally access the eeprom after reset and download initialization information before responding to pci or local bus transactions. a wide variety of available i 2 c-compatible serial components are available to the local and host processor when connected through this interface. the CY7C09449PV local bus is a flexible, configurable inter- face that is designed to readily connect to many industry stan- dard microprocessors. in most cases, no external interface logic ( ? glue ? ) is needed. the following block diagram illustrates a generic application for the CY7C09449PV. operations registers i 2 o message transport unit 128 kb dual-port shared memory i 2 c user-configurable target interfac (supports burst mode) up to 16 kbyte burst transfers on pci bus bus master/slave interface provides required fifos and interrupt status registers allows local processor direct access to pci bus pci 2.2 bus interface pci bus local bus an3042_bd.vs pci-dp local processor bus interface scl/sda tm
CY7C09449PV-ac document #: 38-06061 rev. *a page 3 of 50 3042app.vsd db 6/02 power quicc, 80x86, dsp, etc. sram, dram, flash, etc. mass storage, atm, special, etc. pci system bus processor local bus processor memory peripherals CY7C09449PV 128k bit shared memory pci add-in card or pci system host
CY7C09449PV-ac document #: 38-06061 rev. *a page 4 of 50 pin configuration ad[9] 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 43 44 160 45 159 46 158 47 157 48 156 49 155 50 154 51 153 52 152 53 151 54 150 55 149 56 148 57 147 58 146 59 145 60 144 61 143 62 142 63 141 64 65 66 67 68 140 69 139 70 138 71 137 72 136 73 135 74 134 75 133 76 132 77 131 78 130 79 129 80 128 81 127 82 126 160-lead tqfp (a160) 125 84 83 42 vdd1 adr[8] adr[7] adr[6] adr[5] adr[4] adr[3] adr[2] vss1 irq_in irq_out vss2 vdd2 rstoutd rstoutd rstout vss3 inta rst clk vssp1 vddp1 gnt req ad[31] ad[29] vssp2 vddp2 ad[28] ad[27] ad[26] ad[25] ad[24] ale select sda scl test_mode ad[30] vssp3 vssp4 vddp5 vddp6 vddp3 c/be [3] idsel ad[23] ad[22] ad[21] ad[20] ad[19] vddp4 ad[18] ad[17] ad[16] c/be [2] nc2 frame irdy trdy vssp5 devsel stop perr nc3 serr par c/be [1] ad[15] vssp6 ad[14] ad[13] ad[12] ad[11] ad[8] nc4 vssp7 vddp7 c/ be [0] ad[7] ad[6] ad[5] ad[4] vssp8 vddp8 ad[3] ad[0] vss4 vdd3 dq[0] dq[1] dq[2] dq[3] dq[4] dq[7] dq[8] dq[9] dq[10] dq[11] dq[12] dq[13] vss6 vdd5 vss5 dq[5] dq[6] vdd4 dq[14] dq[15] dq[16] dq[17] dq[18] dq[19] dq[20] vss7 be [1] be [0] rdy_out rdy_in vss8 dq[21] vdd6 pclkout0 vss12 dq[22] dq[23] dq[24] dq[25] dq[26] dq[27] dq[28] vdd7 dq[29] dq[30] dq[31] vss9 blast read write pclkout1 pclkout2 vss10 clkin vss11 vdd8 be [3] be [2] strobe adr[14] adr[13] adr[12] adr[11] adr[10] adr[9] rdy_in nc1 ad[10] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 41 for CY7C09449PV top view ad[1] ad[2]
CY7C09449PV-ac document #: 38-06061 rev. *a page 5 of 50 pin description the pin type for CY7C09449PV is defined as follows: in input is a standard input-only signal. out standard output driver. t/s three-state is an output or bidirectional signal. s/t/s sustained three-state is an active low, three-state capable signal driven by only one bus agent at a time. when ownership is passed to another agent, the signal is driven high for one clock, and then three-stated for an additional clock before being driven by the new owner. o/d open drain signals allow multiple devices to share the pin as a wired-or. o/c open collector signals allow multiple devices to share the pin as a wired-or. pci bus signals signal name type description clk in clock: this is the pci bus clock and is the timing reference for all pci bus transactions. the CY7C09449PV can operate with a 33-mhz pci bus interface. rst in reset: this signal is the pci bus reset. it is one of the few pci signals which may be asserted or deasserted asynchronously to the pci bus clock (clk). ad[31:0] t/s address and data: these signals represent the pci bus address and data signals multiplexed on the same pci pins. information on these pins is identified as an address during the clock cycle in which the signal frame is first asserted. this is termed the ? address phase ? of a bus transaction. information on these pins represents valid read or write data when both irdy and trdy are asserted, based on the current cycle type as defined on the c/be lines during the address phase. this condition is termed the ? data phase ? of a bus transaction. c/be [3:0] t/s command and byte enables: these pins are used with the ad[31:0] pins. during the address phase of a bus operation, they identify the bus command to be performed. during the data phase of a bus operation they identify which bytes are involved. par t/s parity: this pci bus pin represents the even parity across the a/d[31:00] and c/be [3:0] pins (36 pins) and is generated with a one clock delay. frame s/t/s cycle frame: this pci bus pin is asserted by the current bus master to signify the beginning of a bus transaction. data transfers may continue in burst mode while frame remains asserted. when frame is deasserted it indicates that the transaction is in the final data phase. irdy s/t/s initiator ready: this signal is driven by the current bus master (initiator) and asserted to indicate its ability to complete the current data phase. data is transferred when both irdy and trdy are asserted, otherwise wait cycles will occur. trdy s/t/s target ready: this signal is driven by the selected bus target and asserted when that target is ready to complete the current data phase. data is transferred when both irdy and trdy are asserted, otherwise wait cycles will occur. stop s/t/s stop: the stop signal is driven by the selected bus target and is asserted when it wishes to cease the current data transaction. idsel in initialization device select: this signal is used to gain access to the pci configuration register space of a given pci bus agent. devsel s/t/s device select: the devsel signal is driven and asserted by the currently selected pci bus target based on the current address and that target ? s assigned address range. bus masters examine this signal to determine whether the desired device is present.
CY7C09449PV-ac document #: 38-06061 rev. *a page 6 of 50 req t/s request: this signal indicates to the bus arbiter that this device wishes to use the bus. it is a point- to-point signal that is driven whenever rst is not asserted. gnt t/s grant: this point-to-point signal indicates that the bus has been granted to the requester. it is driven whenever rst is not asserted and is ignored during the assertion of rst . perr s/t/s parity error: this signal indicates that a parity error has occurred. it is driven by the target or master that is the receiver of data at the clock after the par signal becomes valid. serr o/d system error: this open drain signal is driven by any device that detects odd parity during an address phase. inta o/d interrupt a: this signal is asserted when interrupt servicing of the CY7C09449PV device is required. the inta pin is a shared pci bus signal and utilizes an open-drain element to allow a wired-or. local bus interface signals signal name type description adr[14:2] in address: these signals identify the local memory location. when the local processor outputs multiplexed address and data, those lines need to be tied to both the dq[14:2] and adr[14:2]. be [3:0] in byte enables: the byte enable inputs identify the specific bytes involved in an access. the pins may be configured as byte lane enables, directly, or used as size and encoded byte lane enables when interfacing to certain motorola processors; see the local bus section for definition. dq[31:0] t/s data: CY7C09449PV data input and output are provided on these bidirectional pins. this bus remains in high impedance during power-up and active reset (rst ) and only drives during read transactions. select in chip select: this signal must be asserted for the full duration of any access. the polarity is pro- grammable; the default is active low. ale in address latch enable: the local address provided on adr[14:2] is latched on the trailing edge (from active to inactive) of this signal. the polarity is programmable; the default is active high. strobe in address strobe: the assertion of this signal begins a memory access and indicates that a valid address has been latched through ale or is provided at the pins (if ale is not used and is tied active). the address is provided on the adr[14:2] pins (during non-multiplexed mode), or on the dq[14:2] (during multiplexed mode). outside the address phase, the level of strobe is don ? t care.the polarity is programmable; the default is active low. write read in write and read signals: these signals control the transfer of data to and from the local data bus. write and read are sampled in the address phase and are don ? t cares during the remainder of the bus transaction. the polarity and function of these signals is programmable so that they can be interfaced to processors that support wr /rd or rd /wr, as well as separate rd/rd and wr/wr signals. blast in burst last: the signal indicates the end of a burst transfer. this signal has two modes. it can be active during the burst and go inactive when the burst is over, or it can go active during the last data phase of the burst. the polarity is programmable; the default is active low. rdy_in rdy_in in ready in: the assertion of these signals indicates that the local processor is prepared to complete the current data transaction. rdy_out out or t/s ready out: when this signal is asserted it indicates that the CY7C09449PV is ready to complete the current access. the polarity is programmable; the default is active low. this signal is also programmable to three-state when inactive; the default is to three-state when inactive. pci bus signals (continued) signal name type description
CY7C09449PV-ac document #: 38-06061 rev. *a page 7 of 50 signal terminations pci bus signals should be terminated according to the pci 2.2 specification. generally, termination is provided by the pci system. if the cy7c09449pc is used as a pci add-in card or other device as part of a pci bus, no termination should be used. for embedded systems, then terminations are part of the system design; they are not particular to the CY7C09449PV. any pci system must include a single pull-up on each pci bus control signal used. these signals are frame , trdy , irdy , devsel , stop , serr , perr , lock , inta , intb , intc , intd , req64 , and ack64 . refer to sec- tion 4.3, system (motherboard) specification, of the pci 2.2 specification for detailed requirements. all local system and local bus interface input signals must be driven at all times. if they are unused inputs, then they may be driven either high or low (pull-up or pull-down, v dd or ground). scl and sda must have a pull-up in the range of 2.2 k ? to 10 k ? to v dd . these pull-ups are required whether the signals are to be used or not. local system signals signal name type description pclkout2 pclkout1 pclkout0 out clock outputs: these pins provide three buffered copies of the pci bus clock. clkin in clock in: this pin provides the timing reference for local bus signals. the clkin pin can be driven by an external clock. also, one of the buffered copies of the pci clock, pclkout[2:0], may be used as input to clkin. this clock must be toggling for proper start-up operation of the CY7C09449PV as well as for pci access to resources other than the dual-ported shared memory. rstout out reset out: this pin provides a buffered version of the pci bus signal, rst . rstoutd rstoutd out reset out delayed: these pins are similar to the rstout pin described above, however rstoutd and rstoutd remain asserted until released by the host interface via software control. this allows the CY7C09449PV to hold the local processor in reset until the host processor is ready to release it. irq_out t/s interrupt request out: this signal may be used to trigger an interrupt on the local microprocessor. a variety of host-triggered events can be used to cause the assertion of this interrupt request output. this signal may be masked using the local interrupt control/status register. when in the inactive state, this signal is three-stated. the polarity is programmable; the default is active low. irq_in in interrupt request in: this signal, when asserted, will result in the CY7C09449PV driving the pci bus inta signal and therefore cause an interrupt of the host system. this signal may be masked using the host interrupt control/status register. test_mode in test mode: when high, this pin puts the CY7C09449PV into a factory test mode. when high and read is low, all outputs are set to high impedance except rdy_out will continue to drive if operations register lbuscfg bit 16 is ? 0 ? . this is the only test mode available to the user. the user must drive this signal low if unused. local configuration signals signal name type description scl o/c serial clock: this pin is the clock output to be used with an external i 2 c-compatible serial memory device. a pull-up resistor is required. sda o/c serial data: this pin is the bidirectional data pin to be used with an external i 2 c-compatible serial memory device. a pull-up resistor is required. power pins signal name type description vssp1 ? vssp8, vss1 ? vss12 gnd ground: these pins are ground pins (0 volts). vddp1 ? vddp8, vdd1 ? vdd8 power power: these pins provide power, nominally 3.3 volts. other pins signal name type description nc1 ? nc4 nc no connect: these pins are not to be used; leave unconnected.
CY7C09449PV-ac document #: 38-06061 rev. *a page 8 of 50 pin list pin name no. pin name no. pin name no. pin name no. vdd1 1 vssp3 41 vddp7 81 vdd6 121 adr[8] 2 c/be [3] 42 c/be [0] 82 dq[21] 122 adr[7] 3 idsel 43 ad[7] 83 dq[22] 123 adr[6] 4 ad[23] 44 ad[6] 84 dq[23] 124 adr[5] 5 ad[22] 45 ad[5] 85 dq[24] 125 adr[4] 6 nc1 46 ad[4] 86 dq[25] 126 adr[3] 7 ad[21] 47 vssp8 87 dq[26] 127 adr[2] 8 ad[20] 48 vddp8 88 dq[27] 128 vss1 9 ad[19] 49 ad[3] 89 dq[28] 129 ale 10 vssp4 50 ad[2] 90 vss8 130 irq_in 11 vddp4 51 ad[1] 91 vdd7 131 irq_out 12 ad[18] 52 ad[0] 92 dq[29] 132 vss2 13 ad[17] 53 vss4 93 dq[30] 133 vdd2 14 ad[16] 54 vdd3 94 dq[31] 134 rstoutd 15 c/be [2] 55 dq[0] 95 vss9 135 rstoutd 16 nc2 56 dq[1] 96 blast 136 rstout 17 frame 57 dq[2] 97 read 137 vss3 18 irdy 58 dq[3] 98 write 138 select 19 trdy 59 dq[4] 99 rdy_in 139 sda 20 vssp5 60 dq[5] 100 rdy_in 140 scl 21 vddp5 61 dq[6] 101 rdy_out 141 test_mode 22 devsel 62 vss5 102 pclkout0 142 inta 23 stop 63 vdd4 103 pclkout1 143 rst 24 perr 64 dq[7] 104 pclkout2 144 clk 25 nc3 65 dq[8] 105 vss10 145 vssp1 26 serr 66 dq[9] 106 clkin 146 vddp1 27 par 67 dq[10] 107 vss11 147 gnt 28 c/be [1] 68 dq[11] 108 vdd8 148 req 29 ad[15] 69 dq[12] 109 be [3] 149 ad[31] 30 vssp6 70 dq[13] 110 be [2] 150 ad[30] 31 vddp6 71 vss6 111 be [1] 151 ad[29] 32 ad[14] 72 vdd5 112 be [0] 152 vssp2 33 ad[13] 73 dq[14] 113 strobe 153 vddp2 34 ad[12] 74 dq[15] 114 adr[14] 154 ad[28] 35 ad[11] 75 dq[16] 115 adr[13] 155 ad[27] 36 ad[10] 76 dq[17] 116 adr[12] 156 ad[26] 37 ad[9] 77 dq[18] 117 adr[11] 157 ad[25] 38 ad[8] 78 dq[19] 118 adr[10] 158 ad[24] 39 nc4 79 dq[20] 119 adr[9] 159 vddp3 40 vssp7 80 vss7 120 vss12 160
CY7C09449PV-ac document #: 38-06061 rev. *a page 9 of 50 memory map CY7C09449PV resources are accessed from the pci bus as an offset from base address register 0 (bar 0), unless oth- erwise indicated. resources are also accessed from the local bus when the select pin is active. pci i/o access to this memory map is also available via pci i/o pointers located at base address register 1 (bar 1). the memory map covers a continuous 32kb address space. pci bus the pci bus of the CY7C09449PV operates per the pci spec- ification revision 2.2. this section describes the specific pci functions supported by the CY7C09449PV. reference url: http://www.pcisig.com/ memory contents address [14:0], byte offset size i 2 o specific registers 0x0000 - 0x03ff 1 kb operations registers 0x0400 - 0x07ff 1 kb reserved 0x0800 - 0x1fff 6 kb direct access to pci bus (this is a window into pci space; this window is only available to the local bus) 0x2000 - 0x3fff 8 kb shared memory 0x4000 - 0x7fff 16 kb pci configuration space pci configuration space 31 16 15 0 address, byte offset device id, ro vendor id, ro 0x00 status, cs command, cs 0x04 class code, ro revision id, ro 0x08 bist (not used) 0x00 header type 0x00 latency timer, rw cache line size, rw 0x0c base address register #0 -- 32kbytes memory space, rw 0x10 base address register #1 -- 8 bytes i/o space, rw 0x14 base address register #2 (not used) 0x0000 0x18 base address register #3 (not used) 0x0000 0x1c base address register #4 (not used) 0x0000 0x20 base address register #5 (not used) 0x0000 0x24 cardbus cis pointer, ro 0x28 subsystem device id, ro subsystem vendor id, ro 0x2c expansion rom base address (not used) 0x0000 0x30 reserved 0x0000 0x34 reserved 0x0000 0x38 max_lat, ro min_gnt, ro interrupt pin, ro interrupt line, rw 0x3c legend for pci configuration space table 0x00 or 0x0000 hardwired to zero ro read-only: may be initialized by eeprom across i 2 c-compatible serial interface cs control and status register rw read/write 23 24 7 8
CY7C09449PV-ac document #: 38-06061 rev. *a page 10 of 50 vendor id address: 0x01 - 0x00 default value: 0x12be read-only: can be initialized from the external memory ac- cessed via the i 2 c-compatible serial interface this 2-byte register contains the vendor id assigned by the pci sig. the default value is the cypress semiconductor ven- dor id. using the i 2 c-compatible serial interface for initializa- tion provides a method to allow a manufacturer to load their own vendor id. device id address: 0x03 - 0x02 default value: 0x3042 read-only: can be initialized from the external memory ac- cessed via the i 2 c-compatible serial interface this 2-byte register contains the device id assigned by the manufacturer. the default value is the CY7C09449PV chip de- vice id. using the i 2 c-compatible serial interface for initializa- tion provides a method to allow a manufacturer to load their own device id. command address: 0x05 - 0x04 default value: 0x0000 read/write this 2-byte register contains bits for device control. these bits are normally set by the system bios. the following bits are supported: bit 0: enable response to i/o space accesses. bit 1: enable response to memory space accesses. bit 2: enable pci bus master operation (may be initialized over the i 2 c-compatible serial interface). bit 3: enable special cycle monitoring, (but CY7C09449PV performs no special function as a target). bit 4: enable bus master use of the memory write and invali- date command. bit 6: enable the perr signal for host notification of data par- ity errors. bit 8: enable the serr signal for host notification of system errors. bit 9: enable fast back-to-back transactions to different agents (but CY7C09449PV does not generate). status address: 0x07 - 0x06 default value: 0x0280 read-only and write-1-to-clear except as indicated. this 2-byte register contains bits for device status. the follow- ing bits are supported: bit 7: read-only bit set to indicate, as a target, the chip can accept fast back-to-back transactions. bit 8: set when perr is asserted. bits 10 and 9: read-only bits set to 0x1 indicating medium response timing for devsel. bit 12: set when, as a master, the chip ? s transaction has been terminated with target-abort. bit 13: set when, as a master, the chip terminates a transac- tion with master-abort. bit 14: set when serr is asserted. bit 15: set whenever a parity error is detected. revision id address: 0x08 default value: 0x02 read-only: can be initialized from the external memory ac- cessed via the i 2 c-compatible serial interface. this 1-byte register contains the revision id assigned by the manufacturer. the default value is set by cypress semicon- ductor at manufacturing time. using the i 2 c-compatible serial interface for initialization provides a method to allow a manu- facturer to load their own revision id. class code address: 0x0b - 0x09 default value: 0x0e0001 read-only: can be initialized from the external memory ac- cessed via the i 2 c-compatible serial interface. this 3-byte register contains the class code assigned by the manufacturer. the default value indicates an i 2 o base class (0x0e), a sub-class of 0x00, and the programming interface that supports system interrupt capability (0x01). using the i 2 c- compatible serial interface for initialization provides a method to allow a manufacturer to load their own class code. cache line size address: 0x0c default value: 0x00 read/write this register contains the cache line size in dwords. the only valid size is 0x08; any other value written will result in a 0x00 being written to the register. the value in this register is used to control when the master can perform memory write and invalidate cycles. additionally, the type of memory read command is determined by this value; (i.e., memory read, memory read line, or memory read multiple). latency timer address: 0x0d default value: 0x00 read/write this register controls how quickly the master must get off the bus if gnt is removed. the CY7C09449PV implements bits [7:3] of this register, providing a granularity of eight clocks. base address register 0 (memory type access) address: 0x13 - 0x10 default value: 0x00000000 read all 32 bits, write bits [31 ? 15]
CY7C09449PV-ac document #: 38-06061 rev. *a page 11 of 50 this register provides the base address of the CY7C09449PV memory map. bits [31 ? 15] are read/write, indicating to the sys- tem bios that the shared memory space is 32 k bytes. if a pci memory transaction has address bits [31 ? 15] matching the contents of this register and memory accesses are en- abled (by command register bit 1), then the CY7C09449PV chip will acknowledge and accept the transfer. base address register 1 (i/o type access) address: 0x17 - 0x14 default value: 0x00000001 read all 32 bits, write bits [31 ? 3] this register provides the base address of the CY7C09449PV i/o pointer space. bits [31 ? 3] are read/write, indicating to the system bios that the i/o pointer space is 8 bytes. if a pci i/o transaction has address bits [31 ? 3] matching the contents of this and i/o accesses are enabled (by command register bit 0), then the CY7C09449PV will acknowledge and accept the transfer. cardbus cis pointer address - 0x2b - 0x28 default value: 0x00000000 read-only: can be initialized from the external memory ac- cessed via the i 2 c-compatible serial interface. this register contains the cardbus card information structure (cis). using the i 2 c-compatible serial interface for initializa- tion provides a method to allow a manufacturer to load their own cis pointer value. subsystem vendor id address: 0x2d - 0x2c default value: 0x0000 read-only: can be initialized from the external memory ac- cessed via the i 2 c-compatible serial interface. this 2-byte register contains the subsystem vendor id chosen by the manufacturer. using the i 2 c-compatible serial interface for initialization provides a method to allow a manufacturer to load their own subsystem vendor id. subsystem device id address: 0x2f - 0x2e default value: 0x0000 read-only: can be initialized from the external memory ac- cessed via the i 2 c-compatible serial interface. this 2-byte register contains the subsystem device id chosen by the manufacturer. using the i 2 c-compatible serial interface for initialization provides a method to allow a manufacturer to load their own subsystem device id. interrupt line address: 0x3c default value: 0x00 read/write this single-byte register contains the interrupt line routing. interrupt pin address: 0x3d default value: 0x00 read-only: can be initialized from the external memory ac- cessed via the i 2 c-compatible serial interface. this single-byte register contains the interrupt pin information. the default value indicates that the CY7C09449PV chip is not connected to the interrupts on the pci bus. using the i 2 c- compatible serial interface for initialization provides a method to allow a manufacturer to specify which interrupt pin is on the bus. only bits [2 ? 0] are implemented. all four interrupt num- bers are supported, (inta through intd ). min_gnt address: 0x3e default value: 0x00 read-only: can be initialized from the external memory ac- cessed via the i 2 c-compatible serial interface. this single-byte register contains the minimum grant time in 1/ 4 microsecond increments needed for efficient operation. the default value indicates the add-in card has no major require- ments for the setting of the latency timer. the latency timer governs how long a burst transaction may use the pci bus. whatever the value, the CY7C09449PV itself does not use the min_gnt data. it is used as a means to communicate system requirements to the host. using the i 2 c-compatible serial in- terface for initialization provides a method to allow a manufac- turer to load their own minimum grant time reflective of their add-in card requirements. max_lat address: 0x3f default value: 0x00 read-only: can be initialized from the external memory ac- cessed via the i 2 c-compatible serial interface. this single-byte register contains the minimum latency time in 1/4 microsecond increments needed for efficient operation. the default value indicates the add-in card has no major re- quirements for how soon it needs access to the pci bus once it has requested an access. whatever the value, the CY7C09449PV itself does not use max_lat data. it is used as a means to communicate system requirements to the host. using the i 2 c-compatible serial interface for initialization pro- vides a method to allow a manufacturer to load their own min- imum latency time reflective of their add-in card requirements. pci bus commands all memory and i/o commands are supported as target and master. i/o read c/be [3:0] = 0x2 i/o write c/be [3:0] = 0x3 memory read c/be [3:0] = 0x6 memory write c/be [3:0] = 0x7 memory read multiple c/be [3:0] = 0xc memory read line c/be [3:0] = 0xe memory write and invalidate c/be [3:0] = 0xf all configuration commands are supported as target and mas- ter. additionally, the CY7C09449PV can perform these ac-
CY7C09449PV-ac document #: 38-06061 rev. *a page 12 of 50 cesses on its own pci configuration space. control originates from the local bus using the CY7C09449PV direct access feature. this is a necessary feature for the CY7C09449PV to perform as a host bridge device. type 0 and type 1 pci con- figuration commands may be generated by the CY7C09449PV. for details, see the direct access and host bridge descriptions in the CY7C09449PV operations section. configuration read c/be [3:0] = 0xa configuration write c/be [3:0] = 0xb interrupt acknowledge and special cycle are supported on master cycles. as a target, no action is performed by the CY7C09449PV. interrupt acknowledgec/be [3:0] = 0x0 special cycle c/be [3:0] = 0x1 the following command is not supported, a target access will result in no response by the CY7C09449PV as per the pci specification. dual-address cycle c/be [3:0] = 0xd the following commands are pci reserved and are not re- sponded to as per pci specification. reserved c/be [3:0] = 0x4 reserved c/be [3:0] = 0x5 reserved c/be [3:0] = 0x8 reserved c/be [3:0] = 0x9 pci i/o pointers utilization of pci i/o access is not generally recommended by the pci special interest group. new system designs should use the pci memory access rather than pci i/o access. in general, this is provided as a support to legacy systems. the CY7C09449PV base address register 1 (bar1) is the offset reference for pci i/o access to this device. i/o address pointer address: 0x1 - 0x0 default value: unknown, not initialized write-only the value written to this location is the offset into the CY7C09449PV memory map. bit 15 is ? don't care. ? i/o data pointer address: 0x7 - 0x4 default value: unknown, not initialized read/write upon a write to the pointer, the data shall be written to the location in the CY7C09449PV memory map specified by the contents of the i/o address pointer. if an i/o read access to the pointer, then the data at the location in the CY7C09449PV memory map which is specified by the contents of the i/o ad- dress pointer shall be returned. local bus general description the CY7C09449PV provides a configurable local processor bus interface which can provide direct connection to several processor types. the interface is synchronous to the clkin signal. the clkin signal can be tied to the local processor's clock, a derivative, or an independent clock source. to run the local interface at pci clock speeds, any one of the pclkout[2:0] pins should be connected to clkin. the basic local processor bus transaction consists of an ad- dress phase, followed by one or more data phases. the inter- face signals are generally divided into those signals that qual- ify the address phase (ale, strobe , select , read , write , and adr[14:2]), and those that qualify data phases, (rdy_in , rdy_in, blast , be [3:0], and dq[31:0]). the CY7C09449PV drives rdy_out to signal the need for wait states on the local processor bus as well as an indication of valid data on dq[31:0] during read access of the CY7C09449PV. note that several of the CY7C09449PV local bus signals have configurable polarity. these are: ale, blast , rdy_out , and strobe . also, the read and write signals have special combined signal modes. the basic local-bus cycle starts with the address phase. the address phase is defined as both strobe and select ac- tive at the rising edge of clkin. also sampled at this time are the read and write signals to determine if the access is a read or write. if the access is a read, then the CY7C09449PV will begin driving the dq bus at the next clkin rising edge. there are two ways to get an address into the CY7C09449PV. with ale tied active, the address is latched during the address phase. that is, when strobe and select are active, the address on the adr[14:2] pins is latched on the rising edge of clkin. the second way is to use the trailing edge of ale to latch the address. the CY7C09449PV still needs a valid ad- dress phase (strobe and select active at the rising edge of clkin) before it will begin processing the address. a valid and stable address must occur before the trailing edge of ale and before the rising edge of clkin where strobe and select are active. after the address phase come wait states and data phases. the strobe signal can be active or inactive during wait and data phases. a data phase occurs when the rdy_in and rdy_in inputs and the rdy_out output are all active at the rising edge of clkin. if any ready signal is inactive, then the next clock cycle is a wait state. the be [3:0] pins are sampled during the data phase of write cycles to determine which data bytes are to be written. the data on the dq pins is also latched at this time. the blast signal is sampled during the data phase to deter- mine if the last data phase is occurring. in one mode, an inac- tive level during the data phase indicates that there are more data phases in the transaction and that the address that was captured in the address phase should be updated. when blast is active during the data phase, it indicates that this is the last data phase of the transaction. in the other mode, blast is active during every data phase and goes inactive at the end of the last data phase. in both cases, if the access is a read, then the CY7C09449PV will stop driving the dq bus synchronously with the rising edge of clkin for that data phase. interface definitions 8-bit interface the 8-bit interface option is selected by setting bits bw[1:0] = '00' in the local bus configuration register. only data lines dq[7:0] are used. the unused portion of the data bus, dq[31:8] must be tied high or low; the bits cannot be left
CY7C09449PV-ac document #: 38-06061 rev. *a page 13 of 50 floating. the least two significant bits of the local address bus should be connected to the byte enable pins be [3:2]. be [0] should be tied to rdy_in which is connected normally. connect be [3] = a1 be [2] = a0 be [1] = logic high be [0] = tie to rdy_in 16-bit interface the 16-bit interface option is selected by setting bits bw[1:0] = '01' in the local bus configuration register. only data lines dq[15:0] are used. the unused portion of the data bus, dq[31:16] must be tied high or low; the bits cannot be left floating. there are two basic modes for 16-bit operation. one is for motorola-style encoded byte enables and the other is for direct byte enables. this is configured with the byte enable mode bit, bemode. there is an exception to the data bus wiring for motorola-style buses if a 32-bit processor bus is con- figured to only use 16 data bits. the upper 16 bits of the pro- cessor bus are connected rather than the lower 16 bits. see the description for bemode='1' below. bemode = '0' is for operation of other than motorola-style byte enables. the table below shows where data on the 16-bit bus is routed within the CY7C09449PV internal data struc- tures. connect be [3] = a1 be [2] = not used, should be tied high be [1] = be1, uds, bhe (byte enable 1, upper data strobe, byte high enable) be [0] = be0, lds, den (byte enable 0, lower data strobe, data enable, a0) notes: be [1:0] are used as byte enables. if the processor always does 16-bit accesses, then these can be tied active low. these byte enables can also be used for upper data strobe (uds) and lower data strobe (lds) for processors which pro- duce these signals. the least significant bit of the local address bus is tied to be [3], and it must be valid during the address phase. this input must be incremented (toggled) at the end of each data phase. bursts to the 16-bit interface do not need to start on a dword boundary. the internal dword address will automatically in- crement after a data phase where be [3] is high. bemode = '1' is for operation of motorola-style byte enables. the tables below show where data on the 16-bit bus is placed in the CY7C09449PV internal data structures. for the case where a 32-bit motorola processor bus is to be configured for 16-bit bus operation, then connect the processor d[31:16] to CY7C09449PV dq[15:0]. for instance, the motorola 68360 processor may be operated in this mode. the tables show this mode of operation. bw[1:0] bemode a1, a0 (be [3], be [2]) dq [7:0] accessed data 00 x 00 data[7:0] 00 x 01 data[15:8] 00 x 10 data[23:16] 00 x 11 data[31:24] bw[1:0 ] be- mode a1 (be [3 ]) dq [15:0] bus accessed data 01 0 0 CY7C09449PV data[15:0] 01 0 1 CY7C09449PV data[31:16]
CY7C09449PV-ac document #: 38-06061 rev. *a page 14 of 50 connect for encoded byte enables be [3] = siz1 (operand transfer size, bit 1) be [2] = siz0 (operand transfer size, bit 0) be [1] = a1 be [0] = a0 bw[1:0] bemode interpretation 01 1 use the following table CY7C09449PV external be [3:0] interpretation -- 'byte' terminology here uses byte 3 as least signifi- cant byte of the processor's internal 32-bit data structure; the signals show pins on the processor. CY7C09449PV internal be [3:0] for writes 0000 all-byte write starting at byte 0 (d[31:16]) (truncated to two bytes) 0011 0001 all-byte write starting at byte 1 (d[23:16]) (truncated to one byte) 1011 0010 all-byte write starting at byte 2 (d[31:16]) (truncated to two bytes) 1100 0011 all-byte write starting at byte 3 (d[23:16]) (truncated to one byte) 1110 0100 single-byte write starting at byte 0 (d[31:24]) 0111 0101 single-byte write starting at byte 1 (d[23:16]) 1011 0110 single-byte write starting at byte 2 (d[31:24]) 1101 0111 single-byte write starting at byte 3 (d[23:16]) 1110 1000 two-byte write starting at byte 0 (d[31:16]) 0011 1001 two-byte write starting at byte 1 (d[23:16]) (truncated to one byte) 1011 1010 two-byte write starting at byte 2 (d[31:16]) 1100 1011 two-byte write starting at byte 3 (d[23:16]) (truncated to one byte) 1110 1100 three-byte write starting at byte 0 (d[31:16]) (truncated to two bytes) 0011 1101 three-byte write starting at byte 1 (d[23:16]) (truncated to one byte) 1011 1110 three-byte write starting at byte 2 (d[31:16]) (truncated to two bytes) 1100 1111 three-byte write starting at byte 3 (d[31:24]) (truncated to one byte) three-byte read starting at byte 3 (d[23:16]) (truncated to one byte) 1110
CY7C09449PV-ac document #: 38-06061 rev. *a page 15 of 50 32-bit interface the 32-bit interface option is selected by setting bits bw[1:0] = ? 10 ? or bw[1:0] = ? 11 ? in the local bus configuration register. data lines dq[31:0] are used. with bw[1:0] = ? 10 ? , the byte enables are used directly as byte write enables. with bw[1:0] = ? 11 ? , however, the meaning of the byte enables is determined from the following tables (based on bemode). for 32-bit processor bus interfaces like the motorola 68020 or 68030, bw = ? 11 ? and bemode = ? 0 ? settings are used. this supports a special style of using byte addressing instead of fully decoded byte enables. the siz1 and siz0 signals of the 68020 are connected to the be [3] and be [2] pins, respectively, and the a1 and a0 signals are connected to the be [1] and be [0] pins on the CY7C09449PV. connect for encoded byte enables be [3] = siz1 (operand transfer size, bit 1) be [2] = siz0 (operand transfer size, bit 0) be [1] = a1 be [0] = a0 for 32-bit processor bus interfaces like the motorola 68040, bw = '11' and bemode = '1' settings are used. this supports a special style of using byte addressing instead of fully decod- ed byte enables. the siz1 and siz0 signals of the 68040 are connected to the be [3] and be [2] pins, respectively, and the a1 and a0 signals are connected to the be [1] and be [0] pins on the CY7C09449PV. a cache-line fill is triggered using the siz1 and siz0 pins on the 68040-type bus. when these bits are set to '11', the CY7C09449PV will interpret this as a burst- of-four, ignoring the burst last signal blast . bw[1:0] bemode interpretation 10 x use byte enables for all 4 byte lanes 11 0 use the following table CY7C09449PV external be [3:0] interpretation -- 'byte' terminology here uses byte 3 as least significant byte of the processor's internal 32-bit data structure; the signals show pins on the processor CY7C09449PV internal be [3:0] for writes 0000 all-byte write starting at byte 0 (d[31:0]) 0000 0001 all-byte write starting at byte 1 (d[23:0]) (truncated to three bytes) 1000 0010 all-byte write starting at byte 2 (d[15:0]) (truncated to two bytes) 1100 0011 all-byte write starting at byte 3 (d[7:0]) (truncated to one byte) 1110 0100 single-byte write starting at byte 0 (d[31:24]) 0111 0101 single-byte write starting at byte 1 (d[23:16]) 1011 0110 single-byte write starting at byte 2 (d[15:8]) 1101 0111 single-byte write starting at byte 3 (d[7:0]) 1110 1000 two-byte write starting at byte 0 (d[31:16]) 0011 1001 two-byte write starting at byte 1 (d[23:8]) 1001 1010 two-byte write starting at byte 2 (d[15:0]) 1100 1011 two-byte write starting at byte 3 (d[7:0]) (truncated to one byte) 1110 1100 three-byte write starting at byte 0 (d[31:8]) 0001 1101 three-byte write starting at byte 1 (d[23:0]) 1000 1110 three-byte write starting at byte 2 (d[15:0]) (truncated to two bytes) 1100 1111 three-byte write starting at byte 3 (d[7:0]) (truncated to one byte) 1110 bw[1:0] bemode interpretation 11 1 use the following table
CY7C09449PV-ac document #: 38-06061 rev. *a page 16 of 50 timing diagrams write cycle a basic write cycle is illustrated below. it includes a burst of three data phases on a 32-bit wide bus. note: 1. this encoding, {bw[1:0], bemode, be[3:2]} = { ? 11111 ? }, results in a burst of four dword. blast should remain active. CY7C09449PV external be [3:0] interpretation -- the signals show pins on the processor CY7C09449PV internal be [3:0] for writes 00xx 32-bit write d[31:0] 0000 0100 8-bit write d[31:24] 0111 0101 8-bit write d[23:16] 1011 0110 8-bit write d[15:8] 1101 0111 8-bit write d[7:0] 1110 100x 16-bit write d[31:16] 0011 101x 16-bit write d[15:0] 1100 11xx [1] burst of four 32-bit writes, blast not used 0000 basic write cycle (burst of three) rwmode = ? 00 ? , asmode = ? 00 ? , bw = ? 10 ? , ddout = ? 0 ? clkin strobe ale select# a = address phase d = data phase w = wait state aw1 w2 w3 d1 w d2 d3 w write# (not used) rdy_in# rdy_out# read# rdy_in dq[31:0] adr[14:2] be#[3:0] blast valid valid valid valid bold indicates output from pci-dp valid valid valid wav1a.vsd 9/11/9 d2 w
CY7C09449PV-ac document #: 38-06061 rev. *a page 17 of 50 read cycle the basic read cycle differs from the write cycle only in the level of the read and write signals, and the timing and driving of the data bus dq. a basic read burst of four data phases on a 32-bit wide bus is illustrated. basic read cycle (burst of four) clkin strobe ale write# (not used) rdy_out# adr[14:2] dq[31:0] valid valid valid read# select# be#[3:0] valid valid valid a = address phase d = data phase w = wait state blast# rwmode= ? 00 ? , asmode= ? 00 ? , bw= ? 10 ? , ddout = ? 0 ? aw1w2d1 d2 w d3 d4 w valid valid valid rdy_in# rdy_in
CY7C09449PV-ac document #: 38-06061 rev. *a page 18 of 50 basic 8-bit interface the following two waveforms illustrate the operation of the 8- bit interface mode. note that only data lines dq[7:0] are used. dq[31:8] are unused and must be tied high or low; they cannot be left floating. the least significant bits of the local address, a[1] and a[0], must be connected to the byte enable pins be [3] and be [2], respectively. these must be valid during the ad- dress phase. in burst operation, be#[3:2] are inputs used at a1 and a0 of the local address bus. bursts to the 8-bit interface do not need to start on a dword boundary. the internal dword address will automatically increment after a data phase where be [3:2] equals ? 11 ? , (a[1:0] = ? 11 ? ). the first waveform illustrates single cycle operation and the second illustrates data burst operation. strobe clkin select# ~ ~ ~ asmode= ? 00 ? , rwmode= ? 00 ? , bw = ? 00 ? , ddout = ? 0 read# write# (not used) ~ ~ rdy_in# ~ rdy_in ~ rdy_out# ~ dq[7:0] blast# adr[14:2] be#[3:2] } pci-dp drives dq bus here ~ ~ ~ ~ be#[1] (not used) ~ be#[0] ~ valid valid valid valid bold indicates output from pci-dp wav6a.vsd 9/11/9 data out data in single data read single data write (high)
CY7C09449PV-ac document #: 38-06061 rev. *a page 19 of 50 basic 16-bit interface the following two waveforms illustrate the operation of the 16- bit interface mode. note that only data lines dq[15:0] are used. dq[31:16] are unused and must be tied high or low; they cannot be left floating. the least significant bit of the local address of the 16-bit bus, a[1], must be connected to the byte enable pin be [3]. it must be valid during the address phase. note that be [1:0] are used as byte enables. if the processor always does 16-bit accesses, then these can be tied active low. these byte enables can also be used for upper data strobe (uds) and lower data strobe (lds) for processors which produce these signals. in burst operation, be [3] must be incremented (toggled) at the end of each data phase. bursts to the 16-bit interface do not need to start on a dword boundary. the internal dword address will automatically increment after a data phase where be [3] equals ? 1 ? , (a[1] = ? 1 ? ). the first waveform illustrates single cycle operation and the second illustrates data burst operation. strobe clkin select# asmode = ? 00 ? , rwmode = ? 00 ? , bw = ? 00 ? , ddout = ? 0 ? read# write# (not used) rdy_in# rdy_in rdy_out# dq[7:0] blast# adr[14:2] be#[3:2] pci-dp drives dq bus here be#[1] (not used) be#[0] bold indicates output from pci-dp internal dword address incremented her data1 data2 data3 data4 00 11 10 01 00 valid wav6b.vsd 9/11/98 (high) valid
CY7C09449PV-ac document #: 38-06061 rev. *a page 20 of 50 strobe clkin select# ~ ~ ~ asmode = ? 00 ? , rwmode = ? 00 ? , bw = ? 00 ? , ddout = ? 0 ? read# write# (not used) ~ ~ rdy_in# ~ rdy_in ~ rdy_out# ~ dq[15:0] blast# adr[14:2] be#[3] } pci-dp drives dq bus here ~ ~ ~ be#[2] (not used) ~ be#[1:0] ~ bold indicates output from pci-dp ~ valid valid valid valid single data read single data write data out data in wav7a.vsd 9/11/9 asmode = ? 00 ? , rwmode = ? 00 ? , bw = ? 01 ? , ddout = ? 0 ?
CY7C09449PV-ac document #: 38-06061 rev. *a page 21 of 50 ale ? address latch enable the ale signal may be used in two modes. with ale tied active, the address is latched during the address phase. that is, when the strobe and select signals are active, the address on the adr[14:2] pins is latched on the rising edge of clkin. the second way is to use the trailing edge of ale to latch the address. the CY7C09449PV still needs a valid ad- dress phase (strobe and select active at the rising edge of clkin) before it will begin processing the address. a valid and stable address must occur before the trailing edge of ale and before the rising edge of clkin where strobe and select are active. the active polarity of ale is defined in the operations registers: ale_pol of the local bus configura- tion register. strobe clkin select# asmode = ? 00 ? , rwmode = ? 00 ? , bw = ? 01 ? , ddout = ? 0 ? read# write# (not used) rdy_in# rdy_in rdy_out# dq[15:0] blast# adr[14:2] be#[3] pci-dp drives dq bus here be#[2] (not used) be#[1:0] bold indicates output from pci-dp data2 data3 data1 data0 valid wav7b.vsd 9/11/98 valid 1 0 1 0 strobe clkin select# strobe clkin select# asmode = ? 00 ? , rwmode = ? 00 ? , bw = ? 01 ? , ddout = ? 0 ? read# write# (not used) rdy_in# asmode = ? 00 ? , rwmode = ? 00 ? , bw = ? 01 ? , ddout = ? 0 ? read# write# (not used) rdy_in# rdy_in rdy_out# rdy_in rdy_out# dq[15:0] blast# adr[14:2] be#[3] pci-dp drives dq bus here be#[2] (not used) be#[1:0] bold indicates output from pci-dp data2 data3 data1 data0 valid wav7b.vsd 9/11/98 valid 1 0 1 0 valid 1 0 1 0 clkin strobe ale adr[14:2] select# address set-up time with respect to rising edge of clkin address set-up time with respect to falling edge of ale cycle start cycle start ale.vsd 9/11/9 valid valid
CY7C09449PV-ac document #: 38-06061 rev. *a page 22 of 50 rdy_out_oe ? ready out three-state mode the rdy_out signal may be configured to drive at all times or to three-state when inactive. the three-state mode is a sus- tained deasserted function. in three-state mode, when rdy_out is to go inactive, rdy_out is driven to the deas- serted level for one clock, and then three-stated. it remains three-stated until rdy_out is to be asserted. the logic polar- ity of rdy_out is programmable. the mode (rdy_out_oe) and polarity (rdyout_pol) controls are set in the local bus configuration register, lbuscfg, of the operations registers. ddout ? delayed data out the delayed data out control defines when the CY7C09449PV drives the dq bus during a local bus read. the control is de- fined in the operations registers: ddout of the local bus configuration register. when ddout = ? 0 ? , the CY7C09449PV will drive the dq bus during a read starting one clock after the address phase and stop driving at the clock edge where both of the ready inputs and blast# are active. when ddout = ? 1 ? , the CY7C09449PV will drive the dq bus during a read starting one clkin clock after the address phase and stop driving one clock after the clock edge where the two ready inputs and blast are active. the data is driven for one clock period after the signal that the transaction is over. in the case of multiple data phases, it adds one clock cycle to the starting latency of the burst. rdy_out ? ready out strobe can be active or inactive during data phases. how- ever, if strobe is active during the data phase when blast is active and the extended ready out control (xtnd_rdy_out) is set, the CY7C09449PV keeps rdy_out active until strobe goes inactive. in the case of a read, the CY7C09449PV will continue to drive the data on dq until strobe is deasserted. read cycle with ddout=1 clkin strobe ale write# (not used) rdy_in# adr[14:2] dq[31:0] valid read# select# bold indicates output from pci-dp be#[3:0] valid a = address phase d = data phase w = wait state blast# rwmode= ? 00 ? , asmode= ? 00 ? , bw= ? 10 ? , ddout= ? 1 ? aw1w2 d rdy_in data output is extended for an extra cycle rdy_out# edout.vsd 9/11/9 valid
CY7C09449PV-ac document #: 38-06061 rev. *a page 23 of 50 line_wrap_dis ? cache line wrap disable this setting is used to disable cache line wrapping, line_wrap_dis = ? 1 ? . cache line wrapping only occurs when the local bus interface is set for 32 bit width with encoded byte enables, using the motorola byte enable encoding, and the bus siz bits indicate a cache line access. specifically, this is when bw = '11', bemode = '0', and be [3] = be [2] = ? 1. ? if a cache line access is made and cache line wrapping is dis- abled, then the burst will proceed linearly with no implicit ad- dress wraparound at the 4 dword boundary. asmode ? address strobe mode the address strobe mode control defines the polarity and the timing used to sample the CY7C09449PV address strobe in- put signal, strobe . the two-bit control field is defined in the operations registers: asmode of the local bus configura- tion register. asmode[0] defines the polarity of the strobe input signal; ? 0 ? = active low and ? 1 ? = active high. asmode[1] controls the sampling edge of the strobe sig- nal. logic low indicates that the signal is sampled using the rising edge of clkin. a logic high indicates that the signal is sampled with the falling edge of clkin. sampling on the fall- ing edge should only be used when the required minimum set- up time with respect to the clock rising edge cannot be met on the signals. the following waveform illustrates the operation of the asmode[1] pin. adr and read are sampled at e2, and a valid write occurs at e4. note that strobe is captured at the negative edge labeled ne1 and that the adr and read sig- nals are sampled at the positive clock edge labeled e2. also note that the ready signals are sampled at the negative edge labeled ne4 and not at the positive edge labeled e5. strobe is active low since asmode[0] = '0. ? extended rdy_out# clkin rdy_in rdy_in# strobe blast# rdy_out# normal rdy_out# when strobe is active at the last data phase, rdy_out# goes inactive after strobe goes inactive. when strobe is inactive at the last data phase, rdy_out# goes inactive at the next clkin edge. rdyout#.vsd 9/11/
CY7C09449PV-ac document #: 38-06061 rev. *a page 24 of 50 falling edge sampling for rdy_in, rdy_in , select , and strobe these signals may be configured for falling edge sampling within the local bus configuration register (lbuscfg) of the operations registers. rdy_in and rdy_in sampling is con- figured by the rdy_in_fall bit, select sampling is config- ured by the select_fall bit, and strobe sampling is con- figured by the asmode[1] bit. setting any one or all of these bits will not effect the sampling of other signals on the local bus. that is, all other signals that are synchronous inputs are sampled on the rising edge of the local bus clock, clkin. when a negative edge sample is used, the other signals are qualified by that sample on the immediately following rising edge of clkin. for example, study the prior waveform illus- trating operation of asmode. in that diagram, strobe is configured to sample on the falling edge of clkin because asmode[1]= ? 1 ? . an active strobe indicates an address phase. the valid address is captured on the first rising clock edge after strobe is sampled active. rwmode ? read write mode the read write mode control defines how the address strobe (strobe ), read (read ), and write (write ) input signals are interpreted by the CY7C09449PV internal logic. the two-bit control field is defined in the operations registers: rwmode of the local bus configuration register. each of the four cases for rwmode are illustrated in the following four diagrams. use rwmode = ? 00 ? to interface to a processor that has a read-write signal defined as w_r (write is logic 1, read is logic 0). in this mode, the write is not used and should be tied high. a write cycle is illustrated below. asmode[1] = ? 1 ? e0 e1 e2 e3 e4 e5 strobe adr[14:2] read# rdy_in# rdy_out# blast# be#[3:0] dq#[31:0] clkin ne1 valid valid valid select# write# asmode[1]= ? 1 ? (32-bit write, single data phase) bold indicates output from pci-dp rwmode= ? 00 ? , asmode= ? 10 ? , bw= ? 10 ? , ddout = ? 0 ? ne4 rdy_in wav3b.vsd 9/11/98
CY7C09449PV-ac document #: 38-06061 rev. *a page 25 of 50 use rwmode = ? 01 ? to interface to a processor that has a read-write signal defined at r_w (write is logic 0, read is logic 1). in this mode, the write acts as r_w and it is sampled when select and strobe are both active. the read pin is not used and should be tied high. this is illustrated below. clkin strobe select# aw d rwmode= ? 00 ? , asmode= ? 00 ? , bw= ? 10 ? , ddout = ? 0 ? write# (not used) read# rdy_in# rdy_in rdy_out# dq[31:0] be#[3:0] blast# valid valid adr[14:2] valid read# (not used) strobe clkin select# write# (acts as w# / r) rdy_in# single data read single data write ~ ~ ~ ~ ~ rwmode= ? 01 ? , asmode= ? 00 ? , bw= ? 10 ? , ddout = ? 0 ? rdy_in ~ ~ rdy_out# ~ dq[31:0] blast# adr[14:2] be#[3:0] } pci-dp drives dq bus here ~ ~ ~ ~ bold indicates output from pci-dp wav5a.vsd 9/11/9 valid data out valid valid data in
CY7C09449PV-ac document #: 38-06061 rev. *a page 26 of 50 use rwmode = ? 10 ? or rwmode = ? 11 ? to interface to a pro- cessor that has separate active low read and write signals. the two modes are identical. sampling of the read and write signals is used as the internal address strobe in place of the strobe signal. this is illustrated below. dq[31:0] blast# valid adr[14:2] be#[3:0] valid valid } pci-dp drives dq bus here ~ ~ ~ ~ clkin select# ~ ~ rwmode= ? 1x ? , asmode= ? 00 ? , bw= ? 10 ? , ddout = ? 0 ? read# write# rdy_out# ~ ~ rdy_in# ~ rdy_in ~ ~ data out data in wav5b1.vsd 10/14/ bold indicates output from pci-dp single data read single data write strobe (not used) ~
CY7C09449PV-ac document #: 38-06061 rev. *a page 27 of 50 i 2 c serial port and auto-configuration the CY7C09449PV i 2 c serial port may master the i 2 c bus, but it is not a target on the bus. read and write access to the port is available to both the pci and local buses via the i 2 c programming operations registers. the CY7C09449PV sup- ports single byte device internal addressing. the port can be used for auto-configuration of the CY7C09449PV as well as for basic read and write access to i 2 c-compatible devices con- nected to the port. auto-configuration is the function that uses the port to load CY7C09449PV configuration information. a typical device containing the data is a serial electrically erasable program- mable read only memory (eeprom). the eeprom in- cludes data for some pci configuration registers and some operations registers. the eeprom containing the CY7C09449PV configuration data must be located at i 2 c de- vice address 0x0 and must contain the proper CY7C09449PV signature. for details, see the memory map below and the accompanying field descriptions. notes: 2. master enable is the most significant bit of this byte; see text for more description of this flag. 3. the recommended value for reserved data in the eeprom is ? 1 ? i 2 c serial port device 0x0 memory map for auto-configuration byte 3 byte 2 byte 1 byte 0 internal address, byte offset don ? t care don ? t care don ? t care don ? t care 0x00 ... 0x3f CY7C09449PV signature 0x48 CY7C09449PV signature 0x37 reserved reserved 0x40 device id high byte device id low byte vendor id high byte vendor id low byte 0x44 class code, base class high byte class code, sub-class middle byte class code, programming intf. low byte revision id 0x48 subsystem device id high byte subsystem device id low byte subsystem vendor id high byte subsystem vendor id low byte 0x4c max_lat min_gnt interrupt pin, master enable [2] don ? t care 0x50 cardbus cis pointer high byte cardbus cis pointer low byte cardbus cis pointer high byte cardbus cis pointer low byte 0x54 reserved reserved reserved reserved 0x58 reserved reserved reserved reserved 0x5c reserved reserved reserved reserved 0x60 reserved reserved reserved reserved 0x64 reserved reserved reserved reserved 0x68 reserved local bus configuration high byte local bus configuration middle byte local bus configuration low byte 0x6c reserved reserved reserved reserved 0x70 host control bits [31:24] host control bits [23:16] host control bits [15:8] host control bits [7:0] 0x74 don ? t care don ? t care don ? t care don ? t care 0xff ? 0x78
CY7C09449PV-ac document #: 38-06061 rev. *a page 28 of 50 CY7C09449PV signature address: 0x43 - 0x42 device configuration signature: a valid eeprom CY7C09449PV configuration image is indicated at this ad- dress by the value of 0x4837. it is read from the eeprom at i 2 c device address 0x0 immediately after the CY7C09449PV comes out of reset. the CY7C09449PV comes out of reset as indicated by the deassertion of the CY7C09449PV rst input. upon recognition of a valid signature, the contents of the eeprom will be transferred to the appropriate CY7C09449PV registers. the appropriate registers are indi- cated by the other labeled fields of the i 2 c serial port device 0x0 memory map for auto-configuration and are described in this section. if the value at this location is not 0x4837, then the transfer will not occur and the default (reset) values for the CY7C09449PV registers will remain in effect after the CY7C09449PV comes out of reset. vendor id address: 0x45 - 0x44 pci configuration vendor id: the meaning of this field is de- scribed in the pci bus section. device id address: 0x47 - 0x46 pci configuration device id: the meaning of this field is de- scribed in the pci bus section. revision id address: 0x48 pci configuration revision id: the meaning of this field is de- scribed in the pci bus section. class code address: 0x4b - 0x49 pci configuration class code (base class, sub-class, pro- gramming interface): the meaning of this field is described in the pci bus section. subsystem vendor id address: 0x4d - 0x4c pci configuration subsystem vendor id: the meaning of this field is described in the pci bus section. subsystem device id address: 0x4f - 0x4e pci configuration subsystem device id: the meaning of this field is described in the pci bus section. interrupt pin address: 0x51, bits 2, 1, 0 pci configuration interrupt pin: the meaning of this field is described in the pci bus section. master enable address: 0x51, bit 7 pci configuration command bit 2: enable pci bus master op- eration. for a host bridge, this typically must be set to allow the host to configure itself and configure and access other de- vices on the pci bus. even though an external master can manipulate the pci command register, it is typical that the host is the first device to configure devices on the pci bus. since the default value for pci command bit 2 is that pci bus mastering is disabled, the master enable bit in the eeprom image should be set to enable pci mastering. min_gnt address: 0x52 pci configuration min_gnt: the meaning of this field is de- scribed in the pci bus section. max_lat address: 0x53 pci configuration max_lat: the meaning of this field is de- scribed in the pci bus section. cardbus cis pointer address: 0x57 - 0x54 pci configuration cardbus cis pointer: the meaning of this field is described in the pci bus section. local bus configuration address: 0x6c - 0x6e operations registers local bus configuration: the detailed meaning of this field is described in the operations registers section. for the CY7C09449PV local bus to exhibit the correct protocol, the local bus configuration operations register needs to be loaded before the CY7C09449PV is accessed via the local bus interface. the local bus interface circuitry will be held in reset until transfer of the eeprom configuration data is complete. at such completion, and dependent upon the state of the host control operations register, the local bus will be available for access using the programmed local bus interface protocol. host control address: 0x77 - 0x74 operations registers host control: only bits 1 and 0 have meaning; the other bits are reserved. when programming bits 1 and 0, other bits of the dword should be written with ? 0 ? . one of two reset controls from the CY7C09449PV may be used to reset the local processor system. the CY7C09449PV rstout output signal is a buffered copy of the pci bus rst signal and is not conditioned by the bits of the host control register. this signal will deassert before the auto-configura- tion process completes, so some applications will not use this signal in order to prevent premature local processor attempts to access the CY7C09449PV. the other form of reset control provides a direct link to the auto-configuration process. using this method, the local pro- cessor will remain in reset until completion of the auto-config- uration process. in this case, the CY7C09449PV rstoutd output signal (or its active high version, rstoutd) is used to reset the local processor. this signal is a copy of bit 0 of the host control register (the local processor reset). with auto- configuration, the local processor will be either held in reset or released from reset depending upon the value in the eeprom. furthermore, as an operations register, the host control register may be accessed from the pci bus once auto- configuration is complete. therefore, if it is desired that the
CY7C09449PV-ac document #: 38-06061 rev. *a page 29 of 50 local processor be held in reset until updated by a command over the pci bus, bit 0 of this field should be set. bit 1 of the host control register should be cleared in most cases. setting it to ? 1 ? will reset the operations registers to their default state and thereby reinitialize the local bus con- figuration register. this bit is typically used only for debug or maintenance operations. another seldom used operation is setting the host control register from the local processor. even though the operations register is available from the local bus, setting either bit 0 or bit 1 to ? 1 ? will lock-out the local processor from accessing the CY7C09449PV by way of the local bus interface. operations registers these registers are the means by which CY7C09449PV func- tions are accessed. access is available via either interface, the pci bus or the local bus. the operations registers include the pci bus mastering registers (dma), the i 2 o messaging unit registers, the interrupt registers, the mail boxes, and the direct access register. also included in the operations regis- ters are the initialization and configuration registers used to customize the CY7C09449PV operation to the user ? s needs. the critical host control register and local bus configuration register may be programmed during the system initialization process. programming via the i 2 c serial is available for this purpose. the operations registers reside in the local bus clock do- main, therefore, a clock must be applied to clkin for proper operation of the CY7C09449PV. either an external clock may be provided or one of the CY7C09449PV pclkout[2:0] sig- nal outputs may be used. pclkout is a copy of the pci clock input, clk. the pclkout signals are intended to be an op- tion for the user to connect to other circuits as well. also available to support other circuits, the user may connect any or all of the three reset outputs from the CY7C09449PV. rstout is a registered copy of the pci reset input, rst . it is synchronous to clkin. the other two reset output signals, rstoutd and rstoutd, are the copy of a bit in an opera- tions register, the ? r ? bit of the host control register. rstoutd and rstoutd are complements of each other and are synchronous to clkin. upon power-up reset of the CY7C09449PV (via the pci reset rst ) this bit will be set active. it may be cleared during the start-up process using the i 2 c serial interface or it may be cleared or set via commands received over the pci bus. therefore, these signals may be used to hold a local processor in reset until CY7C09449PV configuration is complete or when a host is ready to release the local processor to begin its operations. operations registers addresses this is a summary table of the CY7C09449PV operations registers. register locations are the offset from the base ad- dress register 0 and are dword aligned. the value shown is the address of the least significant byte of the register offset. default, power-up values are also shown. both numbers are documented in hexadecimal notation. bit positions in gray are unused and read back as ? 0 ? unless otherwise indicated in the default value.
CY7C09449PV-ac document #: 38-06061 rev. *a page 30 of 50 operations register offset / mnemonic 31 24 23 16 15 8 7 0 default value i 2 o host interrupt status register 0x0030 i2ohisr i 0x00000000 i 2 o host interrupt mask register 0x0034 i2ohimr m 0xffffffff i 2 o local interrupt status register 0x0038 i2olisr i 0x00000000 i 2 o local interrupt mask register 0x003c i2olimr m 0xffffffff i 2 o fifo access all default as empty fifo, read as 0xffffffff inbound free fifo (read only) and inbound post fifo (write only) 0x0040 ibfpfifo outbound post fifo (read only) and outbound free fifo (write only) 0x0044 obpffifo inbound post fifo (read only) and inbound free fifo (write only) 0x0048 ibpffifo outbound free fifo (read only) and outbound post fifo (write only) 0x004c obfpfifo direct access 0x0460 dahbase pci physical base address (4 gbyte, 8 kb blocks) f a1a0 be for reads pci 0xxxxxxxxx i 2 c serial command register (write only) 0x04a0 nvcmd device address memory address write data tr n/a i 2 c serial read data register 0x04a4 nvread byte 3 byte 2 byte 1 byte 0 0xxxxxxxxx i 2 c serial status register 0x04a8 nvstat ack d 0x000000xx dma local base address register 0x04b0 dmalbase local base address (16 kbyte) 0x0000xxxx dma host base address register 0x04b4 dmahbase pci base address (4 gbyte) 0xxxxxxxxx dma burst size register 0x04b8 dmasize dma burst size (16k byte) 0x0000xxxx dma control register 0x04bc dmactl lp pi w 0x0000000x arbitration utility flag register 0x04c0 arbutil l 3 p 3 l 2 p 2 l 1 p 1 l 0 p 0 0x00000000 host control 0x04e0 hctl s r 0x00000001 host interrupt control/status 0x04e4 hint interrupt enable interrupt status 0x00000000 host to local data mailbox 0x04e8 hldata i byte 1 byte 0 0x0000xxxx local processor interrupt control/status 0x04f4 lint interrupt enable interrupt status 0x00000000 local to host data mailbox 0x04f8 lhdata i byte 1 byte 0 0x0000xxxx local bus configuration 0x04fc lbuscfg local bus configuration 0x00010b50
CY7C09449PV-ac document #: 38-06061 rev. *a page 31 of 50 operations registers descriptions detailed descriptions of the operations registers follow. reg- ister locations are the offset from the base address register 0 and are dword aligned. the value shown is the address of the least significant byte of the register offset. the offsets are documented in hexadecimal notation. unused bits are grayed-out. unused bits are read as ? 0 ? unless otherwise indi- cated. i 2 o registers i 2 o host interrupt status register - i2ohisr0x0030 i 2 o host interrupt mask register - i2ohimr0x0034 i 2 o local interrupt status register - i2olisr0x0038 i 2 o local interrupt mask register - i2olimr0x003c 31 30 i bit description 3 -- i interrupt from the outbound post fifo ? the fifo is not empty. this bit is continuously updated to reflect the status of the fifo. it is read-only; ? 0 ? : no interrupt; ? 1 ? : interrupt signalled. '0' default. note: unused bits in this register are read as 0s. 31 30 m bit description 3 -- m host interrupt mask bit 1: interrupt is masked (default) 0: interrupt is not masked note: unused bits in this register are read as 1s. 31 30 i bit description 3 -- i interrupt from the inbound post fifo ? the fifo is not empty. this bit is continuously updated to reflect the status of the fifo. it is read-only; ? 0 ? : no interrupt; ? 1 ? : interrupt signalled. '0' default. note: unused bits in this register are read as 0s. 31 30 m bit description 3 -- m local interrupt mask bit 1: interrupt is masked (default) 0: interrupt is not masked note: unused bits in this register are read as 1s.
CY7C09449PV-ac document #: 38-06061 rev. *a page 32 of 50 i 2 o inbound free / post fifo ? ibfpfifo0x0040 i 2 o outbound post / free fifo ? obpffifo0x0044 i 2 o inbound post / free fifo ? ibpffifo0x0048 i 2 o outbound free / post fifo ? obfpfifo0x004c 31 0 inbound free fifo (read only) and inbound post fifo (write only) bit description 31:0 a shared port -- reading from this port returns data from the inbound free fifo. the read of an empty fifo returns 0xffff ffff. writing to this port places data into the inbound post fifo. if the fifo is already full, the contents of the fifo will not change; the data written will be lost. the fifo is initially empty. an asserted rst# empties all CY7C09449PV fifo; all data will be lost. 31 0 outbound post fifo (read only) and outbound free fifo (write only) bit description 31:0 a shared port -- reading from this port returns data from the outbound post fifo. the read of an empty fifo returns 0xffff ffff. writing to this port places data into the outbound free fifo. if the fifo is already full, the contents of the fifo will not change; the data written will be lost. the fifo is initially empty. an asserted rst empties all CY7C09449PV fifo; all data will be lost. 31 0 inbound post fifo (read only) and inbound free fifo (write only) bit description 31:0 a shared port -- reading from this port returns data from the inbound post fifo. the read of an empty fifo returns 0xffff ffff. writing to this port places data into the inbound free fifo. if the fifo is already full, the contents of the fifo will not change; the data written will be lost. the fifo is initially empty. an asserted rst empties all CY7C09449PV fifo; all data will be lost. 31 0 outbound free fifo (read only) and outbound post fifo (write only) bit description 31:0 a shared port -- reading from this port returns data from the outbound free fifo. the read of an empty fifo returns 0xffff ffff. writing to this port places data into the outbound post fifo. if the fifo is already full, the contents of the fifo will not change; the data written will be lost. the fifo is initially empty. an asserted rst empties all CY7C09449PV fifo; all data will be lost.
CY7C09449PV-ac document #: 38-06061 rev. *a page 33 of 50 direct access register direct access host physical base address register - dahbase0x0460 i 2 c serial port registers i 2 c serial command register -- nvcmd (a write only register)0x04a0 31 13 11 9 8 7 4 2 1 0 pci physical base address (4g byte, 8k byte blocks) f a1a0 byte enables for reads type bit description 31:13 pci physical base address specifying 8 kbyte block 11 -- f when ? 1 ? , force contents of a1a0 to pci during the pci address phase. 9:8 value to be placed on pci bus, pci a1 = bit 9, pci a0 = bit 8. 7:4 data byte enables for pci master reads, c/be#[3:0]. 2:1 type pci command cycle type for pci master access 00 = interrupt acknowledge (read) (pci command 0x0) or special cycle (write) (pci command 0x1) 01 = i/o cycle (read or write) (pci command 0x2 or 0x3) 10 = memory cycle (read or write) (pci command 0x6 or 0x7) 11 = configuration cycle (read or write) (pci command 0xa or 0xb) 31 30 24 23 16 15 87 10 device address memory address write data tr bit description 30:24 device address. device address of the i 2 c serial device. default is 1010000. 23:16 memory address. address within the i 2 c serial device. 15:8 write data. write data. this data is ignored if the command is a read. 1 -- t read type. this bit is ignored if the command is a write. the data read from a i 2 c serial device is accessible from the nvread register. 1 = 4-byte read 0 = single-byte read 0 -- r read / write 1 = read command 0 = write command note: the write of this byte triggers the start of the eeprom access. in an 8- or 16-bit system, this location must be written after the address and data have been written.
CY7C09449PV-ac document #: 38-06061 rev. *a page 34 of 50 i 2 c serial read data register -- nvread0x04a4 this register contains one or four bytes of data read from the i 2 c serial eeprom. i 2 c serial status register ? nvstat0x04a8 this register contains status information about the i 2 c serial data transfer. 31 24 23 16 15 87 0 byte 3 byte 2 byte 1 byte 0 bit description 31:24 byte 3 stores sequential read, byte 3. undefined for single byte read. 23:16 byte 2 stores sequential read, byte 2. undefined for single byte read. 15:8 byte 1 stores sequential read, byte 1. undefined for single byte read. 7:0 byte 0 stores single read and sequential read, byte 0. 31 87 54 0 ack d bit description 7:5 -- ack acknowledge bit 7 = device address ack bit. 0 = ack, 1 = no ack. bit 6 = address ack bit. 0 = ack, 1 = no ack. bit 5 = second address ack bit. 0 = ack, 1 = no ack. in a successful read or write, these bits will be 000. 0 -- d done indicator 1 = done 0 = in progress
CY7C09449PV-ac document #: 38-06061 rev. *a page 35 of 50 pci bus mastering (dma) registers dma local base address register ? dmalbase0x04b0 dma host physical base address register ? dmahbase0x04b4 dma size register ? dmasize 0x04b8 dma control register ? dmactl0x04bc 31 14 13 20 local base address (16k byte) bit description 13:2 local base address - this is the first address of the dma in the local memory. this register has dword resolution. 31 20 pci physical base address (4 gbyte) bit description 31:2 pci physical base address - this is the first address of the dma in the host ? s memory space. this register has dword resolution. 31 14 13 20 dma burst size (16k byte) bit description 13:2 burst size for any mastered dma, read or write. this register has dword resolution. 31 10 9 8 7 2 1 0 lp pi w bit description 9 -- l local ownership: writing to this bit by the local processor will update the value if and only if the p bit is not set to ? 1. ? a write to this bit from the pci bus will never update this bit. this bit (along with the p bit) is intended to facilitate software arbitration of the dma registers. '0' default. 8 -- p pci ownership: writing to this bit by the pci bus will update the value if and only if the l bit is not set to ? 1 ? . a write to this bit from the local processor will never update this bit. this bit (along with the l bit) is intended to facilitate software arbitration of the dma registers. '0' default. 1 -- pi pre-fetch inhibit for pci memory reads: when this bit is set to one, the CY7C09449PV pci bus master engine will only use the pci read command (0x6). when this bit is zero (default), the CY7C09449PV pci bus master engine will use pci commands read (0x6), read line (0xc), and read multiple (0xe) as appropriate to optimize utilization of the pci system bus(es). 0 -- w write: determines the direction of the dma and starts transfer. 1: dma operation is a write to the pci bus memory from the CY7C09449PV shared memory. 0: dma operation is a read from the pci bus memory into the CY7C09449PV shared memory. a write to the low byte of this register triggers the dma to occur. '0' default.
CY7C09449PV-ac document #: 38-06061 rev. *a page 36 of 50 arbitration utility flag register ? arb_flags0x04c0 host control and status registers host control register ? hctl0x04e0 this register contains two types of reset bits. the local pro- cessor reset bit, r, is intended for use by circuitry connected to the cy7c09449 local bus. the output signals rstoutd and rstoutd are a direct reflection of the state of this bit. it is intended that rstoutd (or its active low version rstoutd ) be connected to the local processor system ? s re- set. r is set to ? 1 ? when the CY7C09449PV reset input is as- serted (rst = ? 0 ? ). after deassertion of rst , r will remain set to ? 1 ? until the CY7C09449PV auto-configuration process has completed and it has been cleared either via the auto-config- uration termination control setting or via the pci bus interface. if rstoutd is not used as the local processor system reset, then it can also be cleared via the local bus interface. the second reset bit is the soft reset bit, s. this is used to reset certain internal registers and states of the CY7C09449PV. it is primarily intended for test and debug op- erations during product development. when s = ? 1, ? it will reset all of the operations registers according to their reset default values with the following exceptions: dmactl (at offset 0x04bc): all bits are reset to ? 0 ? , except bits pl and w remain unchanged hint (at offset 0x04e4): all bits remain unchanged lint (at offset 0x04f4): bit 3 (host to local mailbox) is cleared to ? 0 ? , all other bits remain unchanged lbuscfg (at offset 0x04fc): all bits remain unchanged additional behavior when s = ? 1 ? is as follows: dq[31:00] is held at high impedance; local bus state machine is held in idle; dma state machine is held in idle; pci bus state machine mastering access is held in idle; and fifo are emptied and flags return to default (empty). 31 25 24 23 18 17 16 15 10 9 8 7 2 1 0 l3 p3 l2 p2 l1 p1 l0 p0 bit description 25 -- l3 l3 ownership: a write to this bit by the local processor will update this bit if and only if the p3 bit is not set to ? 1 ? . '0' default. 24 -- p3 p3 ownership: a write to this bit by the pci bus will update this bit if and only if the l3 bit is not set. '0' default . 17 -- l2 l2 ownership: a write to this bit by the local processor will update this bit if and only if the p2 bit is not set to ? 1 ? . '0' default. 16 --p2 p2 ownership: a write to this bit by the pci bus will update this bit if and only if the l2 bit is not set. '0' default . 9 -- l1 l1 ownership: a write to this bit by the local processor will update this bit if and only if the p1 bit is not set to ? 1 ? . '0' default. 8 -- p1 p1 ownership: a write to this bit by the pci bus will update this bit if and only if the l1 bit is not set. '0' default. 1 -- l0 l0 ownership: a write to this bit by the local processor will update this bit if and only if the p0 bit is not set to ? 1 ? . '0' default. 0 -- p0 p0 ownership: a write to this bit by the pci bus will update this bit if and only if the l0 bit is not set. '0' default. 31 210 sr bit description 1 -- s soft reset ? this bit controls the internal reset for the CY7C09449PV. 1 = reset active 0 = not reset (default) 0 -- r local processor reset ? this bit controls the rstoutd and rstoutd pins. 1 = reset active (default state, rstoutd pin is low, rstoutd pin is high) 0 = not reset (rstoutd pin is high, rstoutd pin is low)
CY7C09449PV-ac document #: 38-06061 rev. *a page 37 of 50 host interrupt control and status register ? hint0x04e4 31 25 24 16 15 10 9 0 interrupt enable interrupt status bit description 25:16 interrupt enable i nterrupt enables 0000000000 =no interrupts are enabled (default) xxxxxxxxx1 =i 2 o local fifo overflow interrupt enabled xxxxxxxx1x =i 2 o pci fifo overflow interrupt enabled xxxxxxx1xx =reserved - always read as 0 xxxxxx1xxx =local to host, mailbox interrupt enabled xxxxx1xxxx =local to host, external signal interrupt enabled xxxx1xxxxx =dma complete interrupt enabled xxx1xxxxxx =i 2 o inbound post fifo not empty interrupt enabled xx1xxxxxxx =i 2 o outbound post fifo not empty interrupt enabled x1xxxxxxxx =pci target abort interrupt enabled 1xxxxxxxxx =pci master abort interrupt enabled note: all enable bits are initially cleared. 9:0 interrupt status interrupt event status 0000000000 = no events active xxxxxxxxx1 =i 2 o local fifo overflow xxxxxxxx1x =i 2 o pci fifo overflow xxxxxxx1xx =reserved - always read as 0 xxxxxx1xxx =local to host mailbox xxxxx1xxxx =local to host external signal interrupt xxxx1xxxxx =dma complete xxx1xxxxxx =i 2 o inbound post fifo not empty (mirror of i2olisr[3] - read only at this address) xx1xxxxxxx = i 2 o outbound post fifo not empty (mirror of i2ohisr[3] - read only at this address) x1xxxxxxxx = pci target abort 1xxxxxxxxx = pci master abort note: when an event status bit is active, writing a ? 1 ? to that bit location will clear the bit except for bits 6 and 7. all event status bits are initially cleared.
CY7C09449PV-ac document #: 38-06061 rev. *a page 38 of 50 host to local data mailbox ? hldata0x04e8 local control and status registers local interrupt control and status register ? lint0x04f4 31 25 24 23 16 15 87 0 i byte 1 byte 0 bit description 24 -- i interrupt to local this bit enables the host to send an interrupt to the local. when it is set to 1 by the host, it triggers a mailbox interrupt to the local processor. the interrupt remains active until it is cleared by writing to the local interrupt control and status register - lint. 0 = inactive 1 = active this bit is write only. 15:8 -- byte 1 7:0 -- byte 0 data byte two bytes of data that can be written by the host and read by the local processor. 31 25 24 16 15 10 9 0 interrupt enable interrupt status bit description 25:16 interrupt enable interrupt enables 0000000000 = no interrupts are enabled (default) xxxxxx xxx1 = i 2 o local fifo overflow interrupt enabled xx xxxx xx1x = i 2 o pci fifo overflow interrupt enabled xx xxxx x1xx = reserved - always read as 0 xx xxxx 1xxx = host to local mailbox interrupt enabled xx xxx1 xxxx = reserved - always read as 0 xx xx1x xxxx = dma complete interrupt enabled xx x1xx xxxx = i 2 o inbound post fifo not empty interrupt enabled xx 1xxx xxxx = i 2 o outbound post fifo not empty interrupt enabled x1 xxxx xxxx = pci target abort interrupt enabled 1x xxxx xxxx = pci master abort interrupt enabled note: all enable bits are initially cleared. 9:0 interrupt status interrupt event status 00 0000 0000 = no events active xx xxxx xxx1 = i 2 o local fifo overflow xx xxxx xx1x = i 2 o pci fifo overflow xx xxxx x1xx = reserved - always read as 0 xx xxxx 1xxx = host to local mailbox xx xxx1 xxxx = reserved - always read as 0 xx xx1x xxxx = dma operation complete xx x1xx xxxx = i 2 o inbound post fifo not empty (mirror of i2olisr[3] - read only at this address) xx 1xxx xxxx = i 2 o outbound post fifo not empty (mirror of i2ohisr[3] - read only at this address) x1 xxxx xxxx = pci target abort 1x xxxx xxxx = pci master abort note: when an event status bit is active, writing a ? 1 ? to that bit location will clear the bit except for bits 6 and 7. all event status bits are initially cleared.
CY7C09449PV-ac document #: 38-06061 rev. *a page 39 of 50 local to host data mailbox ? lhdata0x04f8 local bus configuration register ? lbuscfg0x04fc 31 25 24 23 16 15 87 0 i byte 1 byte 0 bit description 24 -- i interrupt to host when this bit is written to 1 by the local processor, it causes a mailbox interrupt to the host. the interrupt will remain active until it is cleared by the host in the host interrupt control and status register - hint 0 = inactive 1 = active this bit is write only. 15:8 -- byte 1 7:0 -- byte 0 data bytes two bytes of data written by the local and read by the host processor. 31 21 20 0 local bus configuration bit description 20 line_wrap_dis: defines the enable for cache line wrapping. 0 = enable cache line wrapping (default)1 = disable cache line wrapping 19 rdy_in_fall: defines the edge of clkin used to sample the rdy_in and rdy_in input signals. 0 = rising edge (default)1 = falling edge 18 select_pol: defines the polarity of the select input signal. 0 = active low (default)1 = active high 17 select_fall: defines the edge of clkin used to sample the select input signal. 0 = rising edge (default)1 = falling edge 16 rdy_out_oe: defines the three-state mode of the rdy_out output signal. 0 = drive all of the time.1 = drive only when asserted active. (default) 15 xtnd_rdy_out: defines the rdy_out output signal relation to the final data phase. 0 = normal. rdy_out goes inactive after the final data phase (default) 1 = extended ready out. rdy_out remains active after the final data phase until the internal address strobe (typically strobe ) goes inactive. (see field rwmode for the defining characteristics of the internal address strobe). -- do not set xtnd_rdy_out = 1 when blastmode = 1. 14 burst_style: defines the data ordering protocol of bursts on the local bus. 0 = normal linear bursts (default)1 = 486 style burst (byte ordering in a burst is 048c; 40c8; 8c04; c840) 13 int_pol: defines the polarity of the irq_out output signal. 0 = active low interrupt to the local processor (default)1 = active high interrupt to the local processor 12 blast_pol: defines the polarity of the blast input signal. 0 = active low (default)1 = active high 11 ale_pol: defines the polarity of the ale input signal. 0 = active low1 = active high (default) 10 rdyout_pol: defines the polarity of the rdy_out output signal. 0 = active low (default)1 = active high 9:8 bw: defines the data bus width of the local processor interface. 00 = 8 bit10 = 32 bit 01 = 16 bit11 = 32 bit with encoded byte enables per motorola protocol (default) 7 blastmode: determines the function of the blast input signal. 0 = blast is active only during the last transaction of the burst (default) 1 = blast is active throughout the entire burst, and goes inactive when with rdy_in or rdy_in become inactive on the last read or write of the burst. -- do not set blastmode = 1 when xtnd_rdy_out = 1. 6 bemode: determines the byte enable encoding for 16 and 32 bit motorola modes. 0 = normal byte enables1 = motorola byte enable encoding. (default)
CY7C09449PV-ac document #: 38-06061 rev. *a page 40 of 50 5:4 rwmode: defines how the read , write , and address strobe input signals are interpreted internally and defines the internal address strobe. the active polarity of strobe is determined by asmode. ? 01 ? is default. 3:2 asmode: bit 2 defines the polarity of strobe input signal. and bit 3 defines the edge of clkin used to sample the internal address strobe (see field rwmode for a defining characteristic of the internal address strobe) x0 = strobe is active low (default)x1 = strobe is active high 0x = internal address strobe rising edge sampled (default)1x = internal address strobe falling edge sampled 1 ddin: delayed data input -- defines protocol for validated input data. 0 = input data is valid during the current cycle when rdy_in, rdy_in , and rdy_out are active. (default) 1 = input data is valid one cycle after when rdy_in, rdy_in , and rdy_out are active. 0 ddout: delayed data output -- defines protocol for validated output data. 0 = output data is valid during current cycle when rdy_in, rdy_in , and rdy_out are active. (default) 1 = output data is valid one cycle after when rdy_in, rdy_in , and rdy_out are active. bit description pin name rwmode = 00 rwmode = 01 rwmode = 1x read w_r not used read data; used as internal strobe write not used r_w write data; used as internal strobe strobe internal address strobe internal address strobe not used as internal address strobe
CY7C09449PV-ac document #: 38-06061 rev. *a page 41 of 50 performance characteristics absolute maximum ratings [4 ] storage temperature .................................. ? 55 c to +125 c ambient temperature under bias................. ? 40 c to +85 c max operating current (i dd ) [5,6 ] ................................250 ma voltage on any v dd pin referenced to v ss .. ? 0.5v to +4.0v voltage on any signal pin referenced to v ss ? 0.5v to +7.0v recommended operating environment ambient operating temperature................... t a 0 c to +70 c supply voltage .........................................v dd +3.0v to +3.6v ground voltage reference .......................................v ss 0.0v f clk (pci clock input frequency)...... clk0 mhz to 33 mhz f clkin (local bus clock input frequency) [7 ] ...clkin0 mhz to 50 mhz recommended operating dc parameters ? pci bus sig- nals the CY7C09449PV is compatible with the pci requirements for 3.3v and 5v signaling. refer to the pci local bus specifi- cation, revision 2.2, as published by the pci special interest group; the url is http://www.pcisig.com/ due to the 5v tolerant nature of the i/o, the i/o are not clamped to vdd. operation of the CY7C09449PV in a pci 5v signaling environment is electrical and timing compatible with the pci specification. in a 3.3v signaling environment, all pci requirements are met except for the output 3.3v clamp, which is in direct conflict with 5v tolerance. the CY7C09449PV com- plies with the pci ac specifications. recommended operating dc parameters ? local signals the recommended operating dc parameters for the local bus are specified here. notes: 4. the voltage on any input or i/o pin can not exceed the power pin during power-up. 5. clk=33 mhz, clkin = 50 mhz, pci and local buses operating at 25% duty cycle. 6. also see operating power characteristics section (page 45). 7. for proper initialization, clkin must toggle more than 300,000 cycles after rst has been deasserted. 8. except that inta is an open drain output. 9. except that irq_out is an open drain output. parameter description condition min. max. unit v ih input high voltage 0.5v dd +5.75v v v il input low voltage ? 0.5 0.3v dd v v ipu input pull-up voltage 0.7v dd v i il input leakage current 0 < v in < v dd 10 a v oh output high voltage [8] i out = ? 0.5 ma 0.9v dd v v ol output low voltage i out = 1.5 ma 0.1v dd v c in input pin capacitance 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel input pin capacitance 8 pf l pin pin inductance 20 nh parameter description condition min. max. unit notes v ih input high voltage 2.0 5.75 v v il input low voltage ? 0.5 0.8 v i il input leakage current 0 < v in < v dd 10 a v oh output high voltage i out = ? 0.8 ma 2.4 v 8 v ol output low voltage i out = 0.8 ma 0.5 v c in input pin capacitance 10 pf c clk clk pin capacitance 5 12 pf l pin pin inductance 20 nh
CY7C09449PV-ac document #: 38-06061 rev. *a page 42 of 50 timing parameters ? pci bus signals the CY7C09449PV is compliant with the pci timing requirements for 3.3v and 5v signaling. refer to the pci local bus speci- fication, revision 2.2, as published by the pci special interest group; the url is http://www.pcisig.com/ timing parameters ? CY7C09449PV buffered pci clock and reset the CY7C09449PV provides copies of the pci clock input, clk, on the pclkout[2:0] pins. the system level function and timing of these outputs are the same as those of the clk input. the CY7C09449PV also provides a registered copy of the pci reset input, rst , on the rstout pin. the pci reset is synchronized to the local bus clock, clkin. rstout will follow rst by no more than two clkin cycles. the detailed timing characteristics of the pclkout[2:0] and rstout signal outputs is shown below. notes: 10. clock frequency may range from nominal dc to 33 mhz. the clock frequency may change at anytime, but must not violate other p arameters of this specification: clock edges must remain monotonic and within the specified clk slew rate and clock high and low times must be no shorter than s pecified clk high and clk low times. 11. output maximum times are evaluated with c l = 50 pf. output minimum times are evaluated with c l = 0 pf. actual test capacitance may vary, but results are correlated to these loads. 12. specification only applies to rising (deasserted) edge of rst . 13. rst is asserted and deasserted asynchronously to clk. 14. 50-pf load. parameter description min. max. unit t cyc clk cycle time [10] 30 ns t high clk high time 11 ns t low clk low time 11 ns clk slew rate 1 4 v/ns t val clk to output for bused signals [11] 211ns t val(req) clk to output for req [11] 212ns t on float to active delay from clk 2 ns t off active to float delay from clk 28 ns t su input set-up time to clk for bused signals 7 ns t su(gnt) input set-up time to clk for gnt 10 ns t hold input hold time to clk 0 ns rst slew rate [12] 50 mv/ns t rst rst active time after power stable 1 ms t rst-clk rst active time after clk stable [13] 100 s t rst-off rst active to output float delay 40 ns t rst-fpca rst high to first pci configuration access 2 25 clocks t rhi-ffa rst high to first frame assertion 5 clocks parameter description min. max. units t pclkout pclkout delay from clk [14] 210ns t rstout clkin to rstout valid [14] 210ns
CY7C09449PV-ac document #: 38-06061 rev. *a page 43 of 50 timing parameters ? local bus signals the parameters for the local bus are specified here. notes: 15. v test = 1.5v. 16. voltage threshold for high is 2.0v; voltage threshold for low is 0.8v. 17. inputs are strobe , select , read , write , rdy_in, rdy_in , be [3:0], dq[31:0], blast, and irq_in . 18. c l = 50 pf. outputs are rdy_out , irq_out , rstoutd, and rstoutd . 19. voltage threshold for high is 2.0v. clk pclkout[2:0] t pclkout t pclkout t rstout t rstout clkin rstout# parameter description min. max. unit t local clkin cycle time (local clock) [15] 20 ns t high clkin high time [16] 40 60 % t low clkin low time [16] 40 60 % t su input set-up time to clkin [17] 8ns t hold input hold time to clkin 3 ns t out clkin to output valid [18] 210ns t on_dq dq[31:0] float to active delay from clkin 2 14 ns t out_dq dq[31:0] output delay from clkin 2 10 ns t off_dq dq[31:0] active to float delay from clkin 2 14 ns t su_adr adr[14:2] input set-up time to clkin 6 t h_adr adr[14:2] input hold time from clkin 3 ns t su_ale adr[14:2] input set-up time to ale 1 t h_ale adr[14:2] input hold time from ale 3 ns t min_ale minimum active pulse width for ale [19] 5ns
CY7C09449PV-ac document #: 38-06061 rev. *a page 44 of 50 timing parameters ? i 2 c serial port bus signals the i 2 c-compatible serial interface is designed for a 100-kb transfer rate. the interface clock is referenced to the local clock, clkin. the table below gives the parameters of the CY7C09449PV ? s i 2 c-compatible serial interface with respect to the number of local clock periods and the equivalent number of microseconds if the clock is run at 50 mhz. the 100-kbit/s rate is accompli shed with a clkin rate of 50 mhz. for clkin rates other than 50 mhz, use the minimum clocks column to calculate the minimum time for each parameter. notes: 20. ? start ? condition is a high-to-low transition on sda while scl is high. 21. ? stop ? condition is a low-to-high transition on sda while scl is high dq[31:0] ale adr[14:2] clkin t high t low t local inputs t su t hold t out outputs t on_dq t off_dq t su_adr t h_adr t h_ale t su_ale t out_dq t min_ale parameter description minimum clocks (clock periods) minimum time (microseconds) t scl_lo low period of scl 250 5.00 t scl_hi high period of scl 250 5.00 t buf bus free time between 'start' & 'stop' [20, 21] 500 10.00 t su_sta set-up time for repeated 'start' [20] 250 5.00 t hd_sta hold time for 'start' 250 5.00 t su_dat set-up time for data 125 2.50 t hd_dat hold time for data 125 5.00 t su_sto set-up time for 'stop' 250 5.00
CY7C09449PV-ac document #: 38-06061 rev. *a page 45 of 50 operating power characteristics operating power and currents for the CY7C09449PV at typical environment are specified here, v dd = +3.3v, temp. = +25 c. notes: 22. clk = 33 mhz, clkin = 50 mhz, pci and local buses operating at 25% duty cycle. this value is typical. 23. clk = 33 mhz, clkin = 0 mhz, pci and local buses are inactive. note that for proper initialization of the CY7C09449PV, clkin must toggle for some number of cycles after rst# is de-asserted. see the section recommended operating environment for the specification of the clkin toggl e parameter. sda scl t scl_hi t scl_lo data ~ t hd_sta t su_dat t hd_dat t buf t su_sto t su_sta parameter description condition max. unit pd power dissipation [22] 720 mw i dd operating current [22] 200 ma i dd_lstatic static local bus clock [23] 40 ma i dd_static static, no clocks 1 ma
CY7C09449PV-ac document #: 38-06061 rev. *a page 46 of 50 CY7C09449PV operations local bus configurations the CY7C09449PV interfaces to several processor families. local bus configurations words for some processors are indi- cated here. these may not be suitable for all applications for a given processor. the specific application ? s local processor subsystem architecture may impact some parameters of the local bus configuration word. the 21-bit local bus configura- tion operations register, lbuscfg, can be written via the i 2 c serial interface upon chip initialization to prepare the CY7C09449PV local bus for the proper interface protocol. processor lbuscfg value motorola power quicc mpc860 (default) 0x010b50 motorola quicc 68360 0x018b18 motorola 68040 (default) 0x010b50 intel i960 0x010a00 intel i486 0x016a00 intel 80186 0x012d21 hitachi sh7708 0x010e11 hitachi h8/3048 0x010d00 texas instruments tms320lc31 0x010a91 pci bus mastering burst transfers between the CY7C09449PV 16-kb shared memory and the pci bus system are performed by the direct memory access (dma) controller. set-up for the dma control- ler is accomplished by programming the operations registers of the CY7C09449PV from either the pci bus interface or the local bus interface. an indication of a completed dma is avail- able by polling an operations register or servicing an interrupt. ownership of the dma controller by either the pci or local bus interfaces is arbitrated by software using the operations reg- isters. the address and transfer size registers operate with dword resolution. the lower two bits of each of the address and trans- fer size fields are ignored. transfers over the pci bus are dword so all four byte enables of the bus are active when transferring data mastered by the CY7C09449PV. the full 32- bit pci address space is supported by the dma controller. the direction of transfer is determined by the ? w ? bit in the dma control register. 'w' is the ? write ? bit and is with respect to the CY7C09449PV ? writing ? to the pci bus. the basic sequence to setup a dma is as follows: 1. enable the interrupt mask for the desired interface if an interrupt on dma completion is required (e.g., lint[21] = 1 will enable the interrupt onto the irq_out pin). 2. load the address for the beginning of the transfer block of CY7C09449PV shared memory. this is the dma local base address register, dmalbase. 3. load the address for the beginning of the transfer block of pci bus space. this is the dma host base address reg- ister, dmahbase. 4. load the size of the transfer block. this is the dma size register, dmasize. 5. to initiate the dma, a write to the least significant byte of the dma control register, dmactl, will start the controller. writing a '1' to bit 0 will transfer data from the CY7C09449PV shared memory, (pointed to by dmalbase), to the pci bus space, (pointed to by dmahbase). this causes write bursts on the pci bus. writing a '0' to bit 0 will transfer the other direction and cause read bursts on the pci bus. the CY7C09449PV bus mastering logic will use the most efficient pci command available for all of its bursts during the transfer. 6. when the dma is complete, lint[5] will be set. if interrupts are enabled for dma completions, then an interrupt will be generated. if not, lint[5] can be polled. an additional option of a pci bus mastered read transfer in- volves setting the option to perform non-prefetchable pci reads during transfers into CY7C09449PV shared memory. this option is set in the dma control register with the pfi flag. also, ownership of the controller can be arbitrated in software with assistance of the l and p bits in the dma control regis- ter; these are the local bus ownership and pci bus owner- ship flags, respectively. see the section CY7C09449PV oper- ations registers for details. i 2 o message unit the i 2 o specification describes a messaging unit consisting of four fifos, a shared memory to store message frames, and an interrupt function. the structure of this unit is described in the i 2 o architecture specification, version 1.5 on pages 4-2 through 4-7. this capability is fully integrated within the CY7C09449PV. reference url: http://www.i2osig.org/ there is no need for external circuitry to manage the fifo operations. if i 2 o functionality is not desired, then the fifos are available for general purpose use. each of the four fifo are 32 dword deep, are accessible from both the pci and local bus interfaces, and can generate interrupts to both bus interfaces. the unit operates in two clock domains, that of the pci bus and that of the local bus. i 2 o message frames for transfer between the pci and the local domains are located within the 16-kbyte CY7C09449PV shared memory, which is a general- purpose dual-port memory. there is no restriction upon where in the 16-kbyte space that the message frames reside, how- ever, to satisfy i 2 o requirements, the message frames must begin at dword boundaries. neither bus's access is depen- dent upon the operational state of the other bus. this is gov- erned by the nature of the CY7C09449PV shared memory. operations of the i 2 o fifo and the i 2 o interrupt functions occur completely within the clock domain of the local bus, however access is available to both the pci and local bus interfaces. from a system perspective, the following diagram illustrates the i 2 o message unit transfer function supported by the CY7C09449PV. the CY7C09449PV is represented by the ? message queues ? block of the diagram and consists of both inbound and outbound queues and the shared memory. for more description of the terminology used in the diagram, refer to the i 2 o architecture specification. reference url: http:// www.i2osig.org/ direct access direct access allows the local processor to access the pci bus directly, bypassing the shared memory. in this mode the local processor can generate the following pci bus master cycles: configuration read c/be [3:0] = 0xa
CY7C09449PV-ac document #: 38-06061 rev. *a page 47 of 50 configuration write c/be [3:0] = 0xb i/o read c/be [3:0] = 0x2 i/o write c/be [3:0] = 0x3 memory read c/be [3:0] = 0x6 memory write c/be [3:0] = 0x7 special cycle c/be [3:0] = 0x1 interrupt acknowledge c/be [3:0] = 0x0 to operate in this mode, the local processor programs the di- rect access register. programming sets the base address for the pci master access and the type of pci command to be generated. then the local processor writes to the direct ac- cess space of the CY7C09449PV memory map. offsets into the direct access region of the memory map are added to the pci base address of the direct access register and become the address for the pci bus master access. the type of pci command generated is defined in the direct access register. a local bus read to the direct access area of the memory map becomes a pci bus master read. likewise, a local bus write to the memory map becomes a pci bus master write. host bridge the CY7C09449PV can be used as a host bridge. the proces- sor on the CY7C09449PV local bus is therefore the host pro- cessor in the system. a host processor configures the other pci devices on the pci bus. the CY7C09449PV provides the i 2 c serial port and auto-configuration mechanism to setup for host bridge operations. most aspects of auto-configuration apply to non-host use of the CY7C09449PV, as well. the CY7C09449PV must master cycles onto the pci bus to be a host bridge. the master enable bit located in the pci configuration space is the means to enable CY7C09449PV pci mastering. since the CY7C09449PV's default value for the master enable bit is deasserted, it is necessary to use the CY7C09449PV auto-configuration mechanism to enable pci mastering. during the power-up reset sequence, the i 2 c serial interface loads data from a non-volatile memory (typically a serial eeprom) to set the master enable bit in the pci con- figuration space. some, but not all, of the pci configuration values are loaded using this mechanism. these values can be read by other devices in the system to identify the host bridge, (e.g., device id, vendor id, class code, etc.). another part of the auto-configuration mechanism is to setup the local bus interface with the host processor and, optionally, provide reset control to the host processor. the local bus configuration register is loaded from the serial eeprom im- age. this will set the protocol of the local interface. the host control register is loaded by the auto-configuration mecha- nism and can control reset to the host processor. utilization of the CY7C09449PV rstoutd output signal, (or its comple- ment, rstoutd), is how the CY7C09449PV can control host processor reset. the host control register image is stored in the serial eeprom and indicates if the reset will remain as- serted or will release after auto-configuration is complete. normally, it should release the host from reset. if it is not re- leased, then an external pci master will be required to release the host processor. finally, the CY7C09449PV uses the direct access function to configure pci devices on the pci bus. the first device that it configures is typically itself. it is important that the master en- able bit is set. without this bit asserted, the CY7C09449PV queues.vsd db 7/15/9 i/o devices iop host processor free list fifo of mfa post list fifo of mfa outbound queue inbound queue message queues inbound message frames mfa = offset from start of iop shared memory 0 1 2 3 5 7 0 1 2 3 4 5 6 6 7 system bus 0 -- target initializes free list with message frame addresses, (mfa) 1 -- initiator gets free mfa 2 -- initiator transfers message into message frame storage area 3 -- initiator completes transfer and signals target by posting mfa 4 -- target is notified when post list becomes non-empty 5 -- target gets mfa of posted messag 6 -- target transfers message out of message frame storage area 7 -- target completes transfer by retur mfa to free list inbound queue processing pci bus iop is target host is initiator (or another iop) outbound queue processing iop is initiator host is target free list fifo of mfa post list fifo of mfa 4 outbound message frames mfa = system address shared memory
CY7C09449PV-ac document #: 38-06061 rev. *a page 48 of 50 cannot configuration itself (or any other devices) via the pci bus. dual-port shared memory in order to perform concurrent target access to shared mem- ory from the pci and local bus interfaces it is generally nec- essary to devise a handshake protocol and/or address access allocation scheme to prevent corrupting memory locations. that is, a location within the CY7C09449PV dual-port memory may be corrupted if a read from one interface occurs simulta- neously with a write from the other interface to that same lo- cation. the CY7C09449PV assists the user in managing con- current access to the shared memory. the CY7C09449PV pci and local bus are high performance interfaces. internal logic performs read pre-fetching in order to maintain a full speed, zero wait-state, burst access to the shared memory. for managing memory access, the CY7C09449PV performs a disconnect or wait for target reads at each 64-byte boundary. if a user is allocating sections of memory to pci and local space and intends to execute simul- taneous access to the shared memory from both interfaces, then this 64-byte boundary can be used to place pci and local sections of memory adjacent to each other. in other words, the CY7C09449PV has special logic that detects incoming burst addresses and will initiate the disconnect or wait at each 64- byte boundary. in this way, if the transaction is to end at the boundary, then no further pre-fetching occurs since time has been given to the master to end the bus transaction. for the pci bus, this is performed by a target disconnect. for the local bus, this is wait states. ordering information ordering code package name package type operating range CY7C09449PV-ac tqfp160 160-pin plastic thin quad flat pack 0 c to +70 c package diagram pin 1 pin 160
CY7C09449PV-ac document #: 38-06061 rev. *a page 49 of 50 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram (continued)
CY7C09449PV-ac document #: 38-06061 rev. *a page 50 of 50 document title: CY7C09449PV-ac 128kb dual-port sram with pci bus controller (pci-dp) document number: 38-06061 rev. ecn no. issue date orig. of change description of change ** 113168 02/14/02 dsg change from spec number: 38-01014 to 38-05172 change from spec number: 38-05172 to 38-06061 *a 122309 12/27/02 rbi power up requirements added to absolute maximum ratings information

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